Self-aligned silicidation for replacement gate process
View Patent ↗A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.
1. A semiconductor device comprising:
a high-K dielectric layer on a substrate;
a metal gate electrode on the high-K dielectric layer;
source/drain regions in the substrate adjacent opposite sides of the metal gate electrode;
a self-aligned nickel (Ni) silicide having a resistivity less than 20 μ-ohm-cm on the source/drain regions, the Ni silicide being formed during deposition of the high-K dielectric layer and formation of the metal gate electrode.
2. The semiconductor device according to claim 1 , wherein the high-K dielectric layer comprises hafnium oxide.
3. The semiconductor device according to claim 1 , wherein the high-K dielectric layer has a thickness of 1.5 to 2.5 nm.
4. The semiconductor device according to claim 1 , wherein the high-K dielectric layer is deposited by atomic layer deposition (ALD) at a temperature of 300° C. to 350° C.
5. The semiconductor device according to claim 1 , wherein the high-K dielectric layer is deposited by metal organic chemical vapor deposition (MOCVD) at a temperature of 450° C. to 550° C.
6. The semiconductor device according to claim 1 , wherein the metal gate electrode comprises tungsten.
7. The semiconductor device according to claim 1 , wherein the metal gate electrode is formed at a temperature of 320° C. to 550° C.
8. The semiconductor device according to claim 1 , wherein the Ni silicide substantially comprises NiSi.
9. The semiconductor device according to claim 1 , wherein the source/drain regions comprise epitaxially formed silicon germanium (SiGe) and/or silicon carbon (SiC) source/drain regions.
10. The semiconductor device according to claim 1 , further comprising gate sidewall spacers between the metal gate electrode and the source/drain regions.
11. A semiconductor device comprising:
a high-K dielectric layer on a silicon substrate between sidewall spacers;
a metal gate electrode on the high-K dielectric layer;
a self-aligned nickel (Ni) silicide having a resistivity less than 20 μ-ohm-cm on the silicon substrate at opposite sides of the metal gate electrode, the Ni silicide being formed by:
forming a Ni/platinum (Pt) alloy layer on the silicon substrate, except between the sidewall spacers;
forming an inter layer dielectric (ILD) over the Ni/Pt alloy layer;
depositing the high-K dielectric layer on the substrate between the sidewall spacers at a temperature of 300° C. to 550° C. to initiate a silicide reaction between the Ni/Pt alloy layer and the underlying silicon substrate; and
forming the metal gate electrode on the high-K dielectric layer at a temperature sufficient to effect a high temperature anneal cycle to form a stable NiSi film.
12. The semiconductor device according to claim 11 , wherein the metal gate electrode comprises tungsten and is formed at a temperature of 320° C. to 550° C.
13. The semiconductor device according to claim 11 , wherein the sidewall spacers comprise a nitride.
14. The semiconductor device according to claim 11 , wherein the ILD comprises silicon dioxide (SiO 2 ).
15. The semiconductor device according to claim 11 , wherein the Ni/Pt alloy comprises 2 atomic % to 4 atomic % of Pt.
16. The semiconductor device according to claim 11 , wherein the high-K dielectric layer comprises hafnium oxide.
17. The semiconductor device according to claim 11 , wherein the high-K dielectric layer has a thickness of 1.5 to 2.5 nm.
18. The semiconductor device according to claim 11 , wherein the Ni silicide substantially comprises NiSi.
19. The semiconductor device according to claim 11 , wherein the source/drain regions comprise epitaxially formed silicon germanium (SiGe) and/or silicon carbon (SiC) source/drain regions.
20. A semiconductor device comprising:
a silicon substrate;
sidewall spacers on the silicon substrate;
a high-K dielectric layer on the silicon substrate between the sidewall spacers;
a tungsten gate electrode on the high-K dielectric layer;
epitaxially formed silicon germanium (SiGe) and/or silicon carbon (SiC) source/drain regions in the substrate adjacent opposite sides of the tungsten gate electrode;
a self-aligned nickel silicide (NiSi) layer having a resistivity less than 20 μ-ohm-cm on the silicon substrate on the source/drain regions, the Ni silicide being formed by:
depositing a Ni/platinum (Pt) alloy layer on the source/drain regions;
depositing an inter layer dielectric (ILD) over the Ni/Pt alloy layer;
depositing the high-K dielectric layer on the substrate between the sidewall spacers at a temperature of 300° C. to 550° C. to initiate a silicide reaction between the Ni/Pt alloy layer and underlying silicon; and
forming the tungsten gate electrode on the high-K dielectric layer at a temperature sufficient to effect a high temperature anneal cycle to form a stable NiSi layer.