Stress enhanced transistor devices and methods of making
View Patent ↗Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.
1. A method of fabricating a transistor device, comprising:
forming a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers;
performing an implantation to form etch stop regions a spaced distance below an implanted top surface of the semiconductor substrate such that a top surface of etch stop regions is disposed below a top surface of the semiconductor substrate;
following forming the etch stop regions, selectively etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate that undercut the dielectric spacers and define a channel region between the recessed regions comprising undercut areas, wherein a bottom of the recessed regions stops on the etch stop regions; and
epitaxially growing source and drain regions in the recessed regions of the semiconductor substrate such that the source and drain regions extend underneath the dielectric spacers into the undercut areas of the channel region.
2. The method of claim 1 , wherein the selectively etching the exposed regions of the semiconductor substrate comprises contacting the semiconductor substrate with a hydroxide etchant to make the sidewalls of the channel region slanted such that the sidewalls extend outwardly from a surface of the channel region toward a recessed surface of the semiconductor substrate, and wherein the epitaxially grown source and drain regions comprise silicon germanium when the transistor device is a PFET or silicon carbide when the transistor device is a NFET.
3. The method of claim 2 , wherein the etching comprises an isotropic, wet etch.
4. The method of claim 1 , wherein the forming the etch stop regions comprises:
implanting a p-type species if the transistor device is a PFET or implanting an n-type species if the transistor device is a NFET; and
annealing the semiconductor substrate.
5. The method of claim 4 , wherein the p-type species comprises boron implanted at an energy of about 10 keV to about 100 keV and a dosage of about 2×e 14 ions/cm 2 to about 2×e 15 ions/cm 2 , boron difluoride implanted at an energy of about 10 keV to about 100 keV and a dosage of about 2×e 14 ions/cm 2 to about 1×e 15 ions/cm 2 , or a combination comprising at least one of the foregoing species.
6. The method of claim 1 , wherein the forming the etch stop regions comprises implanting silicon, germanium, carbon, xenon, or a combination comprising at least one of the foregoing species.