Self-aligned silicidation for replacement gate process
View Patent ↗A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.
1. A method of fabricating a semiconductor device, the method comprising:
forming a replaceable gate electrode on a silicon-containing substrate;
forming source/drain regions in the substrate adjacent opposite sides of the replaceable gate electrode;
forming a metal layer on the source/drain regions and the replaceable gate electrode;
forming an inter layer dielectric (ILD) over the metal layer on the source/drain regions;
removing the replaceable gate electrode, thereby forming a cavity;
depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicide reaction between the metal layer and silicon of the silicon-containing substrate underlying the metal layer and concurrently initiating the silicide reaction; and
forming a metal gate electrode on the high-K dielectric layer.
2. The method according to claim 1 , comprising forming a layer of nickel (Ni) and platinum (Pt) alloy as the metal layer.
3. The method according to claim 2 , comprising depositing the high-K dielectric at a temperature of 300° C. to 550° C.
4. The method according to claim 3 , comprising depositing the high-K dielectric at a temperature sufficient to form NiSi.
5. The method according to claim 4 , comprising forming the metal gate electrode at a temperature sufficient to effect a high temperature anneal cycle to form a stable NiSi film.
6. The method according to claim 5 , comprising forming the metal gate electrode at a temperature of 320° C. to 550° C.
7. The method according to claim 1 , comprising:
forming dielectric sidewall spacers on the gate electrode prior to forming the source/drain regions; and
forming the cavity between the sidewall spacers.
8. The method according to claim 1 , comprising epitaxially forming silicon germanium (SiGe) and/or silicon carbon (SiC) source/drain regions.
9. The method according to claim 1 , comprising conformally depositing a Ni and Pt alloy layer on the source/drain regions and the replaceable gate electrode as the metal layer.
10. The method according to claim 9 , further comprising polishing the metal gate electrode.
11. The method according to claim 10 , wherein the silicide reaction forms a silicide with a portion of the Ni and Pt, the method further comprising removing the ILD to expose the silicide after polishing the metal gate electrode.
12. The method according to claim 1 , further comprising polishing the ILD down to the top of the replaceable gate electrode after forming the ILD.
13. The method according to claim 11 , further comprising removing remaining Ni and Pt, which has not reacted with underlying silicon, after removing the ILD.
14. The method according to claim 13 , further comprising depositing a second ILD over the entire substrate after removing the unreacted Ni and Pt.
15. A method of fabricating a semiconductor device, the method comprising:
forming a polysilicon gate electrode on a substrate;
forming sidewall spacers on the gate electrode;
epitaxially forming silicon germanium (SiGe) and/or silicon carbon (SiC) source/drain regions in the substrate adjacent opposite sides of the gate electrode;
depositing a nickel (Ni) and platinum (Pt) layer on the source/drain regions and the gate electrode;
forming an inter layer dielectric (ILD) on the source/drain regions;
polishing the ILD down to the top of the polysilicon gate electrode;
removing the polysilicon gate electrode, thereby forming a cavity between the sidewall spacers;
depositing a high-K dielectric layer at a temperature of 300° C. to 550° C. in the cavity, thereby initiating a silicide reaction between a portion of the Ni and Pt of the Ni and Pt layer and the underlying source/drain regions, forming a silicide on the source/drain regions;
forming a metal gate electrode at a temperature of 320° C. to 550° C. on the high-K dielectric layer;
removing the ILD to expose the silicide; and
removing remaining Ni and Pt of the Ni and Pt layer which has not reacted with the underlying source/drain regions.