Methods for fabricating semiconductor devices
View Patent ↗Embodiments of methods for fabricating the semiconductor devices are provided. The method includes forming a layer of spacer material over a semiconductor region that includes a first gate electrode structure and a second gate electrode structure. Carbon is introduced into a portion of the layer covering the semiconductor region about the first gate electrode structure or the second gate electrode structure. The layer is etched to form a first sidewall spacer about the first gate electrode structure and a second sidewall spacer about the second gate electrode structure.
1. A method for fabricating a semiconductor device, the method comprising
forming a layer of spacer material over a semiconductor region that includes a first gate electrode structure and a second gate electrode structure;
introducing carbon into a portion of the layer covering the semiconductor region about the first gate electrode structure or the second gate electrode structure at a dose of from about 1×10 11 to about 1×10 13 ions·cm −2 and at an accelerating voltage of from about 1 to about 5 KeV to increase an etching rate of the portion to be about 10 to about 25% greater than an etching rate of a portion of the layer not implanted with carbon; and
etching the layer to form a first sidewall spacer about the first gate electrode structure and a second sidewall spacer about the second gate electrode structure.
2. The method according to claim 1 , wherein forming the layer includes forming the layer of the spacer material that is selected from the group consisting of silicon oxide, silicon nitride, and combinations thereof.
3. The method according to claim 1 , wherein introducing carbon includes introducing carbon into the portion of the layer by performing an ion implantation process.
4. The method according to claim 1 , wherein introducing carbon includes introducing carbon into the portion of the layer at the dose of about 1×10 12 ions·cm −2 and an accelerating voltage of about 3 KeV.
5. The method according to claim 1 , wherein etching the layer includes wet etching the layer using a dilute acid solution.
6. The method according to claim 5 , wherein etching the layer includes wet etching the layer using a dilute solution of hydrofluoric acid.
7. The method according to claim 1 , wherein etching the layer includes dry etching the layer by performing a plasma etching process.
8. The method according to claim 1 , wherein etching the layer includes etching the portion implanted with carbon and the portion not implanted with carbon to form the first sidewall spacer having a different width then the second sidewall spacer.
9. A method for fabricating a semiconductor device, the method comprising
forming a layer of spacer material over a semiconductor region that includes a first gate electrode structure and a second gate electrode structure;
masking a first portion of the layer covering the semiconductor region about the first gate electrode structure with masking material;
implanting carbon into a second portion of the layer covering the semiconductor region about the second gate electrode structure at a dose of from about 1×10 11 to about 1×10 13 ions·cm −2 and at an accelerating voltage of from about 1 to about 5 KeV to increase an etching rate of the second portion to be about 10 to about 25% greater than an etching rate of the first portion;
removing the masking material from the first portion; and
blanket etching the layer to form a first sidewall spacer about the first gate electrode structure and a second sidewall spacer about the second gate electrode structure, wherein the first sidewall spacer is wider than the second sidewall spacer.
10. The method according to claim 9 , wherein forming the layer includes forming the layer of the spacer material that is selected from the group consisting of silicon oxide, silicon nitride, and combinations thereof.
11. The method according to claim 9 , wherein implanting carbon includes implanting carbon into the second portion of the layer using an ion implantation process.
12. The method according to claim 9 , wherein implanting carbon includes implanting carbon into the second portion of the layer at the dose of about 1×10 12 ions·cm −2 and an accelerating voltage of about 3 KeV using an ion implantation process.
13. The method according to claim 9 , wherein forming the layer includes forming the layer of the spacer material over the semiconductor region that includes the first gate electrode structure of a N-type transistor and the second gate electrode structure of a P-type transistor, and wherein implanting carbon includes implanting carbon into the second portion of the layer covering the semiconductor region about the second gate electrode structure of the P-type transistor.
14. The method according to claim 13 , further comprising:
forming N-type source and drain extensions and Halo implants into the semiconductor region adjacent to the first sidewall spacer; and
forming P-type source and drain extensions and Halo implants into the semiconductor region adjacent to the second sidewall spacer.
15. The method according to claim 9 , wherein forming the layer includes forming the layer of the spacer material over the semiconductor region that includes the first gate electrode structure of a P-type transistor and the second gate electrode structure of a N-type transistor, and wherein implanting carbon includes implanting carbon into the second portion of the layer covering the semiconductor region about the second gate electrode structure of the N-type transistor.
16. The method according to claim 15 , further comprising:
forming P-type source and drain extensions and Halo implants into the semiconductor region adjacent to the first sidewall spacer; and
forming N-type source and drain extensions and Halo implants into the semiconductor region adjacent to the second sidewall spacer.