Double patterning process for integrated circuit device manufacturing
View Patent ↗A method of forming an integrated circuit (IC) device feature includes forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned; forming a first photoresist layer over the hardmask layer; patterning a first set of semiconductor device features in the first photoresist layer; registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the first photoresist layer; forming a second photoresist layer over the substantially planar hardmask layer; patterning a second set of semiconductor device features in the second photoresist layer; registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the second photoresist layer; and creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device features.
1. A method of forming an integrated circuit (IC) device feature, the method comprising:
forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned;
forming a first photoresist layer over the initially substantially planar hardmask layer, and patterning a first set of semiconductor device features in the first photoresist layer;
registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar;
removing the first photoresist layer;
forming a second photoresist layer over the substantially planar hardmask layer, and patterning a second set of semiconductor device features in the second photoresist layer;
registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar;
removing the second photoresist layer; and
creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device features.
2. The method of claim 1 , wherein registering the first and second sets of semiconductor device features comprises subjecting exposed portions of the initially substantially planar hardmask to a dopant species that creates an etch selectivity within the hardmask layer.
3. The method of claim 2 , wherein the dopant species comprises one or more of germanium, silicon, argon, xenon, and arsenic.
4. The method of claim 2 , wherein creating topography within the hardmask layer comprises a selective etch to remove doped portions of the hardmask layer.
5. A method of forming an integrated circuit (IC) device feature, the method comprising:
forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned;
forming a first photoresist layer over the initially substantially planar hardmask layer, and patterning a first set of semiconductor device features in the first photoresist layer;
registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar;
removing the first photoresist layer;
forming a second photoresist layer over the substantially planar hardmask layer, and patterning a second set of semiconductor device features in the second photoresist layer;
registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar;
removing the second photoresist layer;
creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device features; and
transferring a resulting combined pattern formed in the hardmask layer into the semiconductor device layer therebeneath.
6. The method of claim 5 , wherein registering the first and second sets of semiconductor device features comprises subjecting exposed portions of the initially substantially planar hardmask to a dopant species that creates an etch selectivity within the hardmask layer.
7. The method of claim 5 , wherein the dopant species comprises one or more of germanium, silicon, argon, xenon, and arsenic.
8. The method of claim 5 , wherein creating topography within the hardmask layer comprises a selective etch to remove doped portions of the hardmask layer.
9. The method of claim 5 , wherein the semiconductor device layer comprises a gate conductor layer.
10. The method of claim 9 , wherein the first set of semiconductor device features comprises a plurality of gate conductor lines and the set of semiconductor device features comprises one or more regions where one or more the plurality of gate conductors are broken.
11. The method of claim 5 , wherein the semiconductor device layer comprises an interlevel dielectric (ILD) layer.
12. The method of claim 11 , wherein the first set of semiconductor device features comprises a plurality of contact vias and the second set of semiconductor device features comprises one or additional contact vias located between individual ones of the plurality of contact vias.
13. The method of claim 5 , wherein the semiconductor device layer comprises a semiconductor substrate.
14. The method of claim 13 , wherein the first set of semiconductor device features comprises a plurality of shallow trench isolation (STI) regions and the second set of semiconductor device features comprises one or additional STI regions located between individual ones of the plurality of STI regions.