Method of fabricating damascene structures
View Patent ↗Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.
1. A method, comprising:
(a) forming a wire in a first dielectric layer on a substrate;
after (a), (b) forming a dielectric barrier layer over said wire and said first dielectric layer;
after (b), (c) forming a second dielectric layer over said barrier layer;
after (c), (d) forming a patterned photoresist layer on a top surface of said second dielectric layer;
after (d), (e) with said patterned photoresist layer in place, performing a first reactive ion etch to etch a trench through said second dielectric layer and not through said barrier layer;
after (e), (f) with said patterned photoresist layer in place, performing a second reactive ion etch to extend said trench through said barrier layer; and
after (f), (g) removing said patterned photoresist layer using a reducing plasma or a non-oxidizing plasma.
2. The method of claim 1 , further including:
filling said trench with an electrical conductor.
3. The method of claim 2 , wherein said electrical conductor comprises copper or tungsten.
4. The method of claim 1 , further including:
forming an electrically conductive liner on (i) all surfaces of said barrier layer, said second dielectric layer, and said first wire that are exposed in said trench and (ii) on a top surface of said second dielectric layer;
filling remaining space in said trench with an electrically conductive core conductor; and
performing a chemical mechanical polish to form a damascene wire by removing excess liner and core conductor so a top surface of said damascene wire is coplanar with said top surface of said second dielectric layer.
5. The method of claim 1 , wherein:
said first and second dielectric layers independently include a material selected from the group consisting of porous or nonporous silicon dioxide (SiO 2 ), porous or nonporous fluorinated SiO 2 (FSG), a low K (dielectric constant) material, porous or nonporous hydrogen silsesquioxane polymer (HSQ), porous or nonporous methyl silsesquioxane polymer (MSQ), porous or nonporous organosilicate glass (methyl doped silica or SiO x (CH 3 ) y or SiC x O y H y or SiCOH), and porous or nonporous polyphenylene oligomer; and
said barrier layer includes a material selected from the group consisting of silicon nitride (Si 3 N 4 ), silicon carbide (SiC), silicon oxy nitride (SiON), silicon oxy carbide (SiOC), silicon carbon nitride (SiCN), and plasma-enhanced silicon nitride (PSiN x ).
6. The method of claim 1 , further including:
filling said trench with an electrically conductive material to form a damascene wire;
wherein an opening in said patterned photoresist layer includes an upper region extending part way through said patterned photoresist layer and lower regions extending completely through said patterned photoresist layer; and
wherein said trench includes an upper region extending part way through said second dielectric layer and a lower region extending the rest of the way through said second dielectric layer.
7. The method of claim 1 , wherein said first reactive ion etch etches said second dielectric layer selectively to said barrier layer.
8. The method of claim 7 , wherein said second reactive ion etch etches said second barrier layer selectively to said wire.
9. A method, comprising:
(a) forming a wire in a first dielectric layer on a substrate;
after (a), (b) forming a dielectric barrier layer over said wire and said first dielectric layer;
after (b), (c) forming a second dielectric layer over said barrier layer;
after (c), (d) forming an antireflective coating on a top surface of said second dielectric layer and forming a patterned photoresist layer on a top surface of said antireflective coating;
after (d), (e) with said patterned photoresist layer in place, removing said antireflective coating where said antireflective coating is not protected by said patterned photoresist layer and then performing a first reactive ion etch to etch a trench through said second dielectric layer and not through said barrier layer;
after (e), (f) with said patterned photoresist layer in place, performing a second reactive ion etch to extend said trench through said barrier layer; and
after (f), (g) removing said patterned photoresist layer and any remaining anti-reflective coating using a reducing plasma or a non-oxidizing plasma.
10. The method of claim 9 , further including:
filling said trench with an electrical conductor.
11. The method of claim 10 , wherein said electrical conductor comprises copper or tungsten.
12. The method of claim 9 , further including:
forming an electrically conductive liner on (i) all surfaces of said barrier layer, said second dielectric layer, and said first wire that are exposed in said trench and (ii) on a top surface of said second dielectric layer;
filling remaining space in said trench with an electrically conductive core conductor; and
performing a chemical mechanical polish to form a damascene wire by removing excess liner and core conductor so a top surface of said damascene wire is coplanar with said top surface of said second dielectric layer.
13. The method of claim 9 , wherein:
said first and second dielectric layers independently include a material selected from the group consisting of porous or nonporous silicon dioxide (SiO 2 ), porous or nonporous fluorinated SiO 2 (FSG), a low K (dielectric constant) material, porous or nonporous hydrogen silsesquioxane polymer (HSQ), porous or nonporous methyl silsesquioxane polymer (MSQ), porous or nonporous organosilicate glass (methyl doped silica or SiO x (CH 3 ) y or SiC x O y H y or SiCOH), and porous or nonporous polyphenylene oligomer; and
said barrier layer includes a material selected from the group consisting of silicon nitride (Si 3 N 4 ), silicon carbide (SiC), silicon oxy nitride (SiON), silicon oxy carbide (SiOC), silicon carbon nitride (SiCN), and plasma-enhanced silicon nitride (PSiN x ).
14. The method of claim 9 , further including:
filling said trench with an electrically conductive material to form a damascene wire;
wherein an opening in said patterned photoresist layer includes an upper region extending part way through said patterned photoresist layer and lower regions extending completely through said patterned photoresist layer; and
wherein said trench includes an upper region extending part way through said second dielectric layer and a lower region extending the rest of the way through said second dielectric layer.
15. The method of claim 9 , wherein said removing said antireflective coating where said antireflective coating is not protected by said patterned photoresist layer is performed using an oxygen RIE process.
16. The method of claim 9 , wherein said first reactive ion etch etches said second dielectric layer selectively to said barrier layer.
17. The method of claim 9 , wherein said second reactive ion etch etches said second barrier layer selectively to said wire.