Method and structure of forming silicide and diffusion barrier layer with direct deposited film on silicon
View Patent ↗A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.
1. A method for producing a semiconductor device having a contact structure, which comprises:
a. providing a device having a silicon (Si) substrate;
b. depositing a metal alloy layer on the Si substrate;
c. thermal annealing the metal alloy layer;
d. forming a metal silicide layer and a diffusion barrier layer simultaneously; and
e. depositing a metal layer on the silicide and barrier layers;
wherein the metal alloy layer comprises Ni and W, or is formed as a composition gradient of Ni and W on the Si substrate.
2. The method according to claim 1 , wherein the Si substrate is made of one selected from the group consisting of monocrystalline Si, polycrystalline Si, doped Si, amorphous Si, Si x Ge 1-x where x is any number satisfying 0<x<1, Si x N 1-x where x is any number satisfying 0<x<1, and SiC.
3. The method according to claim 1 , wherein the metal layer deposited on the metal silicide and barrier layers is Cu, Ni, Co, Ag, or Au.
4. The method according to claim 1 , wherein the diffusion barrier layer has a thickness of about 0.1 to 10 nm.
5. The method according to claim 1 , wherein the metal alloy layer has a thickness of about 1 to 1,000 nm.
6. The method according to claim 1 , wherein the metal alloy layer has a thickness of 10 to 200 nm.
7. The method according to claim 1 , wherein the metal alloy layer is annealed at a temperature of about 100° C. to 1,000° C., with 200° C. to 600° C. being more typical.
8. The method according to claim 1 , wherein the metal alloy layer is annealed at a temperature of 200° C. to 600° C.
9. The method according to claim 1 , wherein the metal alloy is formed by electrodeposition, e-beam evaporation, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), or sputtering.
10. The method according to claim 1 , wherein the semiconductor device is a complementary metal oxide silicon (CMOS) logic device, a memory device, an embedded memory device, or a photovoltaic cell.
11. The method according to claim 1 , wherein the metal silicide layer is a nickel silicide layer.