Test macro for use with a multi-patterning lithography process
View Patent ↗A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region and forming a first and second source/drain regions in the active area. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region. The method further includes determining if an overlay shift has occurred during the formation of the active area by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.
1. A method for forming an integrated circuit having a test macro using a multiple patterning lithography process, the method comprising:
forming an active area of the test macro of the integrated circuit;
forming a first gate region in the active area during a first step of the multiple patterning lithography process;
forming a first source/drain region in the active area during a second step of the multiple patterning lithography process;
forming a second source/drain region in the active area during a third step of the multiple patterning lithography process;
forming a third source/drain region in the active area during a fourth step of the multiple patterning lithography process; forming a first contact configured to connect to the first gate region, a second contact configured to connect to the first source/drain region, a third contact configured to connect to the second source/drain region, and a fourth contact configured to connect to the third source/drain region; and
determining if an overlay shift occurred during the multiple patterning lithography process by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.
2. The method of claim 1 , wherein the active region comprises a bulk finFET.
3. The method of claim 1 , wherein the active region includes a transistor having a half-pitch dimension of less than 14 nanometers.
4. The method of claim 1 , wherein the active region includes a transistor having a half-pitch dimension of less than 12 nanometers.
5. The method of claim 1 , wherein the test macro is formed in a scrap area of the integrated circuit.
6. The method of claim 1 , wherein a location of the overlay shift is determined based on the testing for the short between one or more of the first contact, the second contact, the third contact, or the fourth contact.
7. The method of claim 1 , further comprising determining which step of the multiple patterning lithography process caused the overlay shift based on the testing for the short between one or more of the first contact, the second contact, the third contact, or the fourth contact.
8. The method of claim 1 , wherein the first step, the second step, the third step and the fourth step of the multiple patterning lithography process are performed sequentially.