Epitaxial semiconductor resistor with semiconductor structures on same substrate

1. A method of forming an electrical device comprising:

providing a substrate including an upper semiconductor layer on a buried dielectric layer, wherein the buried dielectric layer is present on a base semiconductor layer;

forming an isolation region in the substrate through the upper semiconductor layer to define at least one semiconductor device region and a resistor device region;

forming semiconductor pillars in the isolation region and the upper semiconductor layer of the resistor device region, wherein each of the semiconductor pillars is formed through the buried dielectric layer and into contact with the base semiconductor layer and each of the semiconductor pillars consists of an epitaxially deposited semiconductor material, and wherein the semiconductor pillars that are present in the resistor device region are laterally surrounded by the upper semiconductor layer and the buried dielectric layer;

forming a back gate structure in the base semiconductor layer of the at least one semiconductor device region, while a block mask is present over the resistor device region, wherein the semiconductor pillars that are present in the isolation region are in contact with the back gate structure and are doped, while the semiconductor pillars that are present in the resistor device region are protected by the block mask and remain undoped; and

epitaxially depositing a raised source region, a raised drain region and an epitaxial semiconductor resistor, wherein the raised source region and the raised drain region are present in the at least one semiconductor device region and the epitaxial semiconductor resistor is present in the resistor device region, wherein the epitaxial semiconductor resistor is in direct contact with the semiconductor pillars present in the resistor device region that remain undoped through which the epitaxial semiconductor resistor is in contact to the base semiconductor layer.

2. The method of claim 1 , wherein the semiconductor pillars are formed using an epitaxial deposition process.

3. The method of claim 1 , wherein the semiconductor pillars that are present in the resistor device region provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer.

4. The method of claim 1 , wherein the forming of the isolation region in the substrate through the upper semiconductor layer to define the at least one semiconductor device region and the resistor device region comprises:

etching an opening through the upper semiconductor layer selective to the buried dielectric layer;

depositing a dielectric material to fill the opening that is through the upper semiconductor layer; and

planarizing an upper surface of the dielectric material to be coplanar with an upper surface of the upper semiconductor layer.

5. The method of claim 1 , wherein the at least one semiconductor device region that is defined by placement of the isolation region includes an n-type semiconductor device region and a p-type semiconductor device region.

6. The method of claim 1 , wherein the epitaxially deposited semiconductor material comprises a semiconductor selected from the group consisting of silicon (Si), silicon germanium (SiGe), germanium (Ge) and combinations thereof.

7. The method of claim 1 , wherein the forming of the back gate structure in the base semiconductor layer of the at least one semiconductor device region comprises:

forming the block mask over the resistor device region, wherein the at least one semiconductor device is exposed; and

ion implanting a dopant for the back gate structure at an energy to implant the dopant through the upper semiconductor layer and the buried dielectric layer to a depth within the base semiconductor layer.

8. The method of claim 7 , wherein after the forming the back gate structure, the block mask is removed, and a dopant implantation mask is formed exposing the semiconductor pillars that are present in the isolation region that are in contact with the back gate structure, wherein the dopant implantation mask is protecting the resistor device region and portions of the at least one semiconductor device region that do not include the semiconductor pillars that are present in the isolation region.

9. The method of claim 1 , wherein a front gate structure is formed on the upper semiconductor layer of the at least one semiconductor device region.

10. The method of claim 9 , wherein a source extension region and a drain extension region are formed in the upper semiconductor layer of the at least one semiconductor device region on opposing sides of the front gate structure.

11. The method of claim 1 , wherein the epitaxially depositing the raised source region, the raised drain region, and the epitaxial semiconductor resistor further comprises in-situ doping, wherein the raised source region, the raised drain region and the epitaxial semiconductor resistor having a same conductivity.

12. The method of claim 11 , wherein the raised source region, the raised drain region and the epitaxial semiconductor resistor are doped to an n-type conductivity, wherein a dopant to provide the n-type conductivity is selected from the group consisting of phosphorus, arsenic, antimony and combinations thereof, or the raised source region, the raised drain region and the epitaxial semiconductor resistor are doped to a p-type conductivity, wherein a dopant to provide the p-type conductivity is selected from the group consisting of boron, indium, gallium and combinations thereof.

13. The method of claim 1 , wherein a dopant concentration of the raised source region, the raised drain region and the epitaxial semiconductor resistor is greater than 1×10 18 atoms/cm 3 .

14. The method of claim 1 , wherein the forming the semiconductor pillars in the isolation region and the upper semiconductor layer of the resistor device region comprises:

forming pillar openings in the isolation region and the resistor device region, wherein the pillar openings in the isolation region extend through the isolation region and the buried dielectric layer to expose portions of the base semiconductor layer, and wherein the pillar openings in the resistor device region extend through the upper semiconductor layer and the buried dielectric layer to expose other portions of the base semiconductor layer; and

filling the pillar openings with the epitaxially deposited semiconductor material to form the semiconductor pillars.