Method and apparatus for angular high density plasma chemical vapor deposition
View Patent ↗Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.
1. A method for fabricating a trench structure in a semiconductor, the method comprising:
providing a semiconductor substrate having at least one trench structure formed therein;
positioning the substrate within an angular deposition tool, wherein the substrate is placed on a pedestal, and wherein the pedestal has an adjustable tilt;
positioning the pedestal at an angle with respect to the deposition direction;
performing an electron filtering operation to enable non-perpendicular deposition;
performing a deposition of spacer material with the substrate at said angle, thereby causing a deposition of spacer material to form on only one side of the trench structure; and
performing an etch, thereby removing excess spacer material, and forming a spacer inside the trench structure.
2. The method of claim 1 , wherein the step of positioning the substrate at an angle comprises positioning the substrate at an angle ranging from about 10 degrees to about 60 degrees.
3. The method of claim 1 , wherein the step of performing an etch comprises performing a reactive ion etch.
4. The method of claim 1 , wherein the step of performing a deposition of spacer material comprises performing a deposition of silicon oxide.
5. The method of claim 1 , wherein the step of performing a deposition of spacer material comprises performing a deposition of silicon nitride.
6. A method for fabricating an asymmetrical spacer on a transistor in a semiconductor, the method comprising:
providing a semiconductor substrate having at least one transistor formed thereon, the transistor comprising a gate;
positioning the substrate within an angular deposition tool, wherein the substrate is placed on a pedestal, and wherein the pedestal has an adjustable tilt, wherein the pedestal holding the substrate is positioned at an angle ranging from about 10 degrees to about 60 degrees with respect to the deposition direction;
performing an electron filtering operation to enable non-perpendicular deposition;
performing a deposition of spacer material with the substrate at said angle, wherein the spacer material is selected from the group consisting of oxide, nitride, and oxynitride, thereby causing more spacer material to be deposited on one side of the gate;
performing an etch, thereby removing excess spacer material, and forming an asymmetrical spacer comprised of a small spacer and a large spacer.
7. The method of claim 6 , wherein the step of performing an etch comprises performing a reactive ion etch.
8. The method of claim 6 , wherein the step of performing a deposition of spacer material comprises performing a deposition of silicon oxide.
9. The method of claim 6 , further comprising the step of performing a second etch, whereby the second etch removes the small spacer.
10. The method of claim 9 , wherein the step of performing a second etch comprises performing an isotropic etch.
11. The method of claim 10 , wherein the step of performing an isotropic etch comprises performing a wet etch.