Silicon germanium heterojunction bipolar transistor having interstitial trapping layer in base region
View Patent ↗A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
1. A heterojunction bipolar transistor (HBT) comprising:
a semiconductor substrate including a collector region;
an intrinsic base region formed on said collector region;
an emitter region; and
an extrinsic base region connected to said intrinsic base and formed on said substrate, said extrinsic base region comprising:
a semiconductor material layer; and
a layer of an interstitial trapping material buried within said semiconductor material layer,
wherein said semiconductor material layer directly contacts the uppermost surface of said interstitial trapping material and
the lowermost surface of said interstitial trapping material directly contacts said semiconductor layer.
2. The HBT of claim 1 , wherein said interstitial trapping material comprises carbon and said intrinsic base region is free of said planar carbon layer.
3. The HBT of claim 1 , wherein said extrinsic base region comprises a plurality of planar layers of said interstitial trapping material.
4. The HBT of claim 1 , wherein said semiconductor material layer is doped with a dopant.
5. The HBT of claim 4 , wherein said dopant comprises boron and at least a portion of said extrinsic base region comprises said planar layer sandwiched between portions of said semiconductor material layer, said portions being above and below the sandwiched portion of said planar layer.
6. The HBT of claim 5 , wherein said extrinsic base region is doped with boron to a solid solubility limit of boron in said semiconductor material.
7. The HBT of claim 1 , wherein said intrinsic base region is a SiGe layer free of said planar layer.
8. The HBT of claim 1 , wherein said emitter region is disposed over said intrinsic base region.
9. An integrated circuit (IC) chip including at least one heterojunction bipolar transistor (HBT), said HBT comprising:
a collector at a surface of a semiconductor material layer;
an intrinsic base region formed on said surface above said collector;
an emitter disposed above said intrinsic base;
a doped extrinsic base connected to said intrinsic base; and
an interstitial barrier buried in said doped extrinsic base,
wherein said extrinsic base directly contacts the uppermost surface of said interstitial barrier and
the lowermost surface of said interstitial barrier directly contacts said extrinsic base.
10. An IC as in claim 9 , wherein said planar interstitial barrier comprises at least one planar layer of interstitial trapping material.
11. An IC as in claim 10 , wherein said at least one layer comprises a plurality of interstitial trapping material layers.
12. An IC as in claim 10 , wherein said interstitial trapping material comprises carbon.
13. An IC as in claim 10 , wherein said interstitial trapping material comprises SiGe:C and said intrinsic base region is free of said planar SiGe:C layer.
14. An IC as in claim 13 , wherein said doped extrinsic base and said intrinsic base comprise SiGe.
15. An IC as in claim 9 , wherein said doped extrinsic base is doped with boron and at least a portion of said extrinsic base region comprises said planar layer sandwiched between portions of said semiconductor material layer, said portions being above and below the sandwiched portion of said planar layer.
16. An IC as in claim 9 , further comprising a silicide layer on said doped extrinsic base.
17. A heterojunction bipolar transistor (HBT) comprising:
a semiconductor substrate including a collector region;
shallow trench isolation (STI) regions in a surface of said semiconductor substrate defining an HBT collector;
an intrinsic base on said HBT collector;
an emitter on said intrinsic base; and
an extrinsic base on said surface and connected to said intrinsic base, said extrinsic base comprising:
a semiconductor material layer doped with a dopant to a solid solubility limit of said dopant in said semiconductor material;
a layer of an interstitial trapping material buried within said semiconductor material layer,
wherein said semiconductor material layer directly contacts the uppermost surface of said interstitial trapping material and
the lowermost surface of said interstitial trapping material directly contacts said semiconductor layer; and
a silicide layer on said semiconductor material layer.
18. The HBT of claim 17 , wherein said semiconductor substrate is a silicon substrate and includes a sub-collector beneath said HBT collector, said intrinsic base is a monocrystalline SiGe layer, said extrinsic base comprises polycrystalline SiGe and a nitride collar on landing pads on said intrinsic base encloses said emitter.
19. The HBT of claim 18 , wherein said interstitial trapping material comprises carbon (SiGe:C), said dopant comprises boron and at least a portion of said extrinsic base region comprises said planar layer sandwiched between portions of said semiconductor material layer, said portions being above and below the sandwiched portion of said planar layer.
20. The HBT of claim 19 , wherein said extrinsic base region comprises a plurality of layers of said interstitial trapping material.