Strained semiconductor devices and methods of fabricating strained semiconductor devices

1. A structure, comprising:

a first region of a semiconductor substrate separated from a second region of said semiconductor substrate by trench isolation formed in said substrate;

a first field effect transistor comprising a first source/drains on opposite sides of a first channel region formed in said first region and a first gate electrode formed over said first channel region; and

a second field effect transistor comprising second source/drains on opposite sides of a second channel region formed in said second region and a second gate electrode formed over said second channel region

a first stressed layer having a first thickness over first gate electrode, said first stressed layer over said first region, said first stressed layer extending over all of said first gate electrode and extending over all of said first source/drains;

a second stressed layer having a second thickness over said second gate electrode, said second stressed layer over second region, said second stressed layer extending over all of said second gate electrode and extending over all of said second source/drains;

said first stressed layer and second stressed layer separated by a gap;

a conformal passivation layer having a third thickness measured over a top surface of said first gate electrode or measured over a top surface of said second gate electrode, said conformal passivation layer directly on top surfaces of said first and second stressed layers and regions of a top surface of said trench isolation in said gap, a top surface of said passivation layer following the contours of said top surfaces of said first and second stressed layers and extending over and sealing said gap, said conformal passivation layer extending over all of said first field effect transistor and all of said second field effect transistor; and

wherein said third thickness is less than said first thickness and said third thickness is less than said second thickness.

2. The structure of claim 1 , wherein said first stressed layer is in tensile stress and said second stressed layer is in compressive stress.

3. The structure of claim 1 , wherein said first stressed layer is silicon nitride in tensile stress and said second stressed layer is silicon nitride in compressive stress.

4. The structure of claim 1 , wherein said conformal passivation layer is silicon nitride.

5. The structure of claim 1 , wherein said first field effect transistor is an NFET and said second second field effect transistor is a PFET; and

wherein said first stressed layer is silicon nitride in tensile stress and said second stressed layer is silicon nitride in compressive stress.

6. The structure of claim 1 , wherein said semiconductor substrate comprises a silicon layer separated from a silicon substrate by a buried oxide layer and said first source/drains, said first channel region, said second source/drains, said second channel region and said trench isolation are formed in said silicon layer.

7. The structure of claim 1 , wherein a first distance between a top surface of said substrate and a top surface of said conformal passivation layer over said first and second stressed regions is greater than a second distance between said top surface of said substrate and said top surface of said conformal passivation layer over said gap.

8. The structure of claim 1 , wherein a thickness of said conformal passivation layer over said gap is less than said first thickness of and less than said second thickness.

9. The structure of claim 1 , wherein said conformal passivation layer is unstressed.

10. The structure of claim 1 , wherein said conformal passivation layer is in a compressive stress less than that of said second stressed layer.

11. The structure of claim 1 , wherein said conformal passivation layer is in a tensile stress less than that of said first stressed layer.

12. The structure of claim 1 , wherein:

said first field effect transistor and second field effect transistors are separated by trench isolation formed in said semiconductor substrate under said gap; and

said first stressed layer overlaps said trench isolation and said second stressed layer overlaps said trench isolation.

13. A method, comprising:

forming a first region of a semiconductor substrate separated from a second region of said semiconductor substrate by trench isolation in said substrate;

forming a first field effect transistor in said first region, said first field effect transistor comprising a first source/drains on opposite sides of a first channel region formed in said first region and a first gate electrode formed over said first channel region; and

forming a second field effect transistor in said second region, said second field effect transistor comprising second source/drains on opposite sides of a second channel region formed in said second region and a second gate electrode formed over said second channel region;

forming a first stressed layer over said first region, said first stressed layer having a first thickness over said first gate electrode;

forming a second stressed layer over second region, said first stressed layer having a first thickness over said second gate electrode, said first and second stressed layers overlapping over said trench isolation, said second stressed layer extending over all of said second gate electrode and extending over all of said second source/drains;

removing said overlapped first and second stressed layers to form a gap separating said first stressed layer from second stressed layer, after said removing (i) said first stressed layer extending over all of said first gate electrode and extending over all of said first source/drains and (ii) said second stressed layer extending over all of said second gate electrode and extending over all of said second source/drains;

forming a conformal passivation layer having a third thickness measured over a top surface of said first gate electrode or measured over a top surface of said second gate electrode directly on top surfaces of said first and second stressed layers and regions of a top surface of said trench isolation in said gap, a top surface of said passivation layer following the contours of said top surfaces of said first and second stressed layers and extending over and sealing said gap, said conformal passivation layer extending over all of said first field effect transistor and all of said second field effect transistor; and

wherein said third thickness is less than said first thickness and said third thickness is less than said second thickness.

14. The method of claim 13 , wherein said first stressed layer is in tensile stress and said second stressed layer is in compressive stress.

15. The method of claim 13 , wherein said first stressed layer is silicon nitride in tensile stress and said second stressed layer is silicon nitride in compressive stress.

16. The method of claim 13 , wherein said conformal passivation layer is silicon nitride.

17. The method of claim 13 , wherein said first source/drains, said first channel region and said first gate electrode comprise an NFET and said second source/drains, said second channel region and said second gate electrode comprise a PFET; and

wherein said first stressed layer is silicon nitride in tensile stress and said second stressed layer is silicon nitride in compressive stress.

18. The method of claim 13 , wherein said semiconductor substrate comprises a silicon layer separated from a silicon substrate by a buried oxide layer and said first source/drains, said first channel region, said second source/drains, said second channel region and said trench isolation are formed in said silicon layer.

19. The method of claim 13 , wherein a first distance between a top surface of said substrate and a top surface of said conformal passivation layer over said first and second stressed regions is greater than a second distance between said top surface of said substrate and said top surface of said conformal passivation layer over said gap.

20. The method of claim 13 , wherein a thickness of said conformal passivation layer over said gap is less than said first thickness of and less than said second thickness.

21. The method of claim 13 , wherein said conformal passivation layer is unstressed.

22. The method of claim 13 , wherein said conformal passivation layer is in a compressive stress less than that of said second stressed layer.

23. The method of claim 13 , wherein said conformal passivation layer is in a tensile stress less than that of said first stressed layer.

24. The method of claim 13 , wherein:

said first field effect transistor and second field effect transistors are separated by trench isolation formed in said semiconductor substrate under said gap; and

said first stressed layer overlaps said trench isolation and said second stressed layer overlaps said trench isolation.