Integrated circuit having back gating, improved isolation and reduced well resistance and method to fabricate same

1. A method of forming a structure, comprising:

providing a semiconductor substrate;

forming a first opening to a first depth in the semiconductor substrate;

amorphizing semiconductor sidewalls of an upper portion of the first opening leaving unamorphized semiconductor sidewalls in a lower portion of the first opening;

enlarging only the lower portion of the first opening using an etch process that is selective to the unamorphized semiconductor sidewalls;

filling the first opening with an insulator material to form a deep trench isolation (DTI) structure; and

implanting a first well region and a second well region into the semiconductor substrate, the first well and the second well being separated from one another by the enlarged lower portion of the first opening.

2. The method of claim 1 , where the first depth is about equal to a depth in the semiconductor substrate to which the first well region and the second well region are implanted.

3. The method of claim 1 , further comprising:

forming a second opening to a second depth in the semiconductor substrate, the second depth being less than the first depth; and

totally amorphizing semiconductor sidewalls of the second opening; where

filling the first opening with an insulator material also fills the second opening to form a shallow trench isolation (STI) structure.

4. The method of claim 3 , where the semiconductor substrate is disposed beneath a buried oxide layer that in turn is disposed beneath a semiconductor layer, where the first opening extends through the semiconductor layer, through the buried oxide layer and into the semiconductor substrate, and where the second opening extends through the semiconductor layer to the buried oxide layer, and where the amorphized upper portion of the first opening is disposed within the semiconductor layer.

5. The method of claim 3 , where the semiconductor substrate is a bulk semiconductor substrate, where totally amorphizing semiconductor sidewalls of the second opening also amorphizes a bottom surface of the second opening.

6. The method of claim 5 , where the amorphized first portion of the first opening extends to a greater depth in the bulk semiconductor substrate than the amorphized sidewalls and bottom surface of the second opening.

7. The method of claim 3 , where amorphizing the semiconductor sidewalls of the upper portion of the first opening and totally amorphizing the semiconductor sidewalls of the second opening is accomplished using an angled ion implant.

8. The method of claim 7 , where the angled ion implant uses one of Xe, In, BF 2 , B 18 H 22 , C 16 H 10 , Si, Ge or As as an implant species.

9. The method of claim 7 , where the angled ion implant uses Xe as an implant species and is performed with about a 10 KeV implant energy and about a 3×10 14 atoms/cm 2 dose.

10. The method of claim 3 , further comprising re-crystallizing the amorphized semiconductor sidewalls of the first and the second openings.

11. The method of claim 10 , where re-crystallizing is accomplished during at least one of an anneal process conducted to densify the insulator material and a dopant activation anneal process conducted after implanting the first and second wells.

12. The method of claim 3 , further comprising forming semiconductor devices over the first and second wells, where the first and second wells function as back gates for the semiconductor devices, and where two adjacent semiconductor devices are separated from one another by the STI.

13. The method of claim 1 , where filling the first opening with an insulator material to form the DTI structure forms a void within the insulator material that fills the lower portion of the first trench.