Method for keyhole repair in replacement metal gate integration through the use of a printable dielectric
View Patent ↗A method of fabricating a FET device is provided that includes the following steps. A wafer is provided. At least one active area is formed in the wafer. A plurality of dummy gates is formed over the active area. Spaces between the dummy gates are filled with a dielectric gap fill material such that one or more keyholes are formed in the dielectric gap fill material between the dummy gates. The dummy gates are removed to reveal a plurality of gate canyons in the dielectric gap fill material. A mask is formed that divides at least one of the gate canyons, blocks off one or more of the keyholes and leaves one or more of the keyholes un-blocked. At least one gate stack material is deposited onto the wafer filling the gate canyons and the un-blocked keyholes. A FET device is also provided.
1. A field effect transistor (FET) device, comprising:
at least one active area formed in a wafer;
gates over the active area, wherein the gates cover portions of the active area that serve as channel regions of the device and wherein portions of the active area that extend out from under the gates serve as source and drain regions of the device;
a dielectric gap fill material in between the gates;
one or more keyholes in the dielectric gap fill material, wherein the keyholes are defined by a gap in the dielectric gap fill material, and wherein the keyholes are present in between the gates and extend parallel to the gates through the dielectric gap fill material;
a mask that i) is perpendicular to the gates and divides at least one of the gates and ii) blocks off one or more of the keyholes by filling at least a portion of one or more of the keyholes;
one or more interconnect structures of the device formed in one or more of the keyholes; and
contacts formed in the dielectric gap fill material, wherein the interconnect structures connect at least two of the contacts.
2. The FET device of claim 1 , wherein the active area further comprises a plurality of fins patterned in the wafer, wherein the gates are present over the fins and cover at least a portion of each of the fins that serve as channel regions of the device and wherein portions of the fins extending out from under the gates serve as source and drain regions of the device.
3. The FET device of claim 1 ,
wherein one or more other of the contacts connect with the source and drain regions of the device.