Deep trench capacitor

1. A deep trench capacitor structure in a semiconductor-on-insulator (SOI) substrate, the structure comprising:

a SOI substrate comprising a SOI layer, a rare earth oxide layer, and a bulk substrate; the rare earth oxide layer being a first epitaxial layer and being located below the SOI layer and above the bulk substrate, and the rare earth oxide layer insulating the SOI layer from the bulk substrate, the SOI layer being a second epitaxial layer; and

a deep trench capacitor extending from a top surface of the SOI layer, through the rare earth oxide layer, down to a location within the bulk substrate,

wherein the rare earth oxide layer contacts the deep trench capacitor at an interface between the rare earth oxide layer and the bulk substrate and from the interface the rare earth oxide layer is inclined away from the deep trench capacitor, at an angle relative to an interface of the deep trench capacitor and the bulk substrate, and

wherein the SOI layer is also inclined away from the deep trench capacitor.

2. The structure of claim 1 , wherein the deep trench capacitor comprises a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between a buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench.

3. The structure of claim 2 , wherein the buried plate comprises a heavily doped region extending from a sidewall and a bottom of the deep trench into the bulk substrate.

4. The structure of claim 1 , wherein the rare earth oxide layer comprises a thickness ranging from about 5 nm to about 50 nm.

5. The structure of claim 1 , wherein the SOI layer comprises a thickness ranging from about 3 nm to about 10 nm.

6. The structure of claim 1 , further comprising:

a semiconductor device adjacent to the deep trench capacitor; and

an electrical connection between a source or drain region of the semiconductor device and an inner electrode of the deep trench capacitor,

wherein the semiconductor device and the deep trench capacitor together form a memory cell.

7. The structure of claim 6 , wherein the electrical connection comprises a contact extending from a top surface of an inter-dielectric layer to the source or drain region of the semiconductor device and the inner electrode of the deep trench capacitor.

8. The structure of claim 6 , further comprising

Forming a logic device adjacent to the semiconductor device.

9. The structure of claim 1 , wherein the rare earth oxide layer and the SOI layer being inclined away from the deep trench capacitor defines a space between the rare earth oxide layer and the deep trench capacitor, and between the SOI layer and the deep trench capacitor, the space being filled with a dielectric material.

10. The structure of claim 1 , wherein the rare earth oxide layer being inclined away from the deep trench capacitor defines a space between the rare earth oxide layer and the deep trench capacitor, the space being filled with a dielectric material.