ENABLING ENHANCED RELIABILITY AND MOBILITY FOR REPLACEMENT GATE PLANAR AND FINFET STRUCTURES

1 . A method for semiconductor fabrication, comprising:

forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity;

performing a first anneal to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer;

forming a cap semiconductor layer over the dielectric layer; and

performing a second anneal after forming said cap semiconductor layer to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

2 . The method of claim 1 , further comprising removing the metal containing layer and the diffusion barrier layer prior to said forming the cap semiconductor layer.

3 . The method as recited in claim 1 , wherein forming includes:

forming a second diffusion barrier layer over the metal containing layer over the dielectric layer in a first device region; and

forming the diffusion barrier layer over the dielectric layer in a second device region.

4 . The method as recited in claim 2 , wherein performing the first anneal includes performing the first anneal to diffuse elements:

from the second diffusion barrier layer and the metal containing layer into the dielectric layer in the first device region; and

from the diffusion barrier layer into the dielectric layer in the second device region.

5 . The method as recited in claim 1 , further comprising:

forming a first semiconductor layer over a first cap diffusion barrier layer over the metal containing layer before performing the first anneal; and

removing the first semiconductor layer and the first cap diffusion barrier layer after performing the first anneal.

6 . The method as recited in claim 1 , further comprising

forming a second semiconductor layer over a second cap diffusion barrier layer over the dielectric layer before performing the second anneal; and

removing the cap semiconductor layer after performing the second anneal.

7 . The method as recited in claim 1 , wherein the dielectric layer includes a hafnium oxide (HfO 2 ) layer formed over a silicon dioxide (SiO 2 ) layer.

8 . The method as recited in claim 6 , wherein performing the first anneal includes performing the first anneal to diffuse the elements through the HfO 2 layer and at least partially though the SiO 2 layer.

9 . The method as recited in claim 7 , wherein performing the second anneal includes performing the second anneal to regrow at least a portion of the SiO 2 layer.

10 . The method as recited in claim 1 , wherein the metal containing layer includes lanthanum oxide (La 2 O 3 ) and the diffusion barrier layer includes titanium nitride (TiN).

11 . The method as recited in claim 1 , further comprising forming at least one workfunction material layer on the dielectric layer.

12 . The method as recited in claim 10 , further comprising forming a conductive layer over the at least one work function material layer to form a replacement gate stack.

13 . A method for semiconductor fabrication, comprising:

forming a second diffusion barrier layer over a metal containing layer over the dielectric layer in a first device region, and a first diffusion barrier layer over a dielectric layer in a second device region;

performing a first anneal to diffuse elements from the second diffusion barrier layer and the metal containing layer into the dielectric layer in the first device region, and from the first diffusion barrier into the dielectric layer in the second device region;

removing the second diffusion barrier, the metal containing layer, and the first diffusion barrier;

forming at least one of a cap semiconductor layer over the dielectric layer; and

performing a second anneal after said forming of said at least one of the cap semiconductor layer to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

14 . The method of claim 13 , further comprising removing the metal containing layer and the diffusion barrier layer prior to said forming the cap semiconductor layer.

15 . The method as recited in claim 13 , wherein the dielectric layer includes a hafnium oxide (HfO 2 ) layer formed over a silicon dioxide (SiO 2 ) layer.

16 . The method as recited in claim 13 , wherein the metal containing layer includes lanthanum oxide (La 2 O 3 ) and the first and second diffusion barrier layers include titanium nitride (TiN).

17 . A method for semiconductor fabrication, comprising:

performing a first anneal to diffuse elements from the at least one of a diffusion barrier layer and a metal containing layer into a dielectric layer that is present in a gate cavity;

removing the metal containing layer and the diffusion barrier layer;

forming a second cap diffusion barrier layer on the dielectric layer after removing said metal containing layer and the diffusion barrier layer; and

performing a second anneal after forming the second cap diffusion barrier layer to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

18 . The method of claim 17 further comprising forming a cap layer over the second cap diffusion layer prior to said performing the second anneal.

19 . The method as recited in claim 17 , wherein the dielectric layer includes a hafnium oxide (HfO 2 ) layer formed over a silicon dioxide (SiO 2 ) layer, and wherein performing the first anneal includes performing the first anneal to diffuse the elements through the HfO 2 layer and at least partially though the SiO 2 layer.

20 . The method as recited in claim 19 , wherein performing the second anneal includes performing the second anneal to regrow at least a portion of the SiO 2 layer.