Structures and methods to enhance Cu interconnect electromigration (EM) performance
View Patent ↗The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in interconnects. A method includes forming an interconnect, forming a cap on the interconnect, and forming a plurality of holes in the cap to improve electromigration performance of the interconnect.
1. A method for forming a semiconductor structure, comprising:
forming an interconnect;
forming a cap on the interconnect;
forming a plurality of holes in the cap, wherein the plurality of holes expose first and second portions of the interconnect and improve electromigration performance of the interconnect;
cleaning the first and second portions of the interconnect exposed by the plurality of holes; and
forming an additional cap layer directly on the first and second portions of the interconnect, wherein the additional cap layer comprises one of doped silicon carbide, silicon nitride, and low k material.
2. The method of claim 1 , wherein the interconnect is composed of copper.
3. The method of claim 1 , wherein the cap comprises one of: doped silicon carbide, silicon nitride, and low k material.
4. The method of claim 1 , wherein the plurality of holes extend through the cap to an upper surface of the interconnect.
5. The method of claim 1 , wherein a distance between two adjacent holes of the plurality of holes is less than a line length below which voids caused by electromigration will not occur.
6. The method of claim 1 , wherein the cleaning comprises bombarding the first and second portions of the interconnect with H 2 ions.
7. The method of claim 1 , wherein:
each one of the plurality of holes comprises a stripe having a length in a width direction of the interconnect when viewed in a top down view;
the length of each stripe is equal to or greater than the width of the interconnect when viewed in the top down view; and
a width of each stripe is equal to or greater than a predetermined line width.
8. The method of claim 1 , wherein:
a distance between two adjacent holes of the plurality of holes is less than a predetermined length; and
the predetermined length is a line length below which voids caused by electromigration will not occur.
9. The method of claim 1 , wherein the interconnect comprises a wide wire having at least one anti-dishing hole, and at least one of the plurality of holes coincides with the at least one anti-dishing hole.
10. The method of claim 1 , further comprising:
forming a second interconnect having a second upper surface on which the cap is arranged; and
forming second plurality of holes in the cap over the second interconnect,
wherein the second plurality of holes are staggered in relation to the plurality of holes.
11. A method of forming a semiconductor structure, comprising:
forming an interconnect;
forming a cap layer on a top surface of the interconnect;
selectively removing a plurality of portions of the cap layer at discrete locations along the top surface of the interconnect spaced apart at a length that is less than a predetermined length; and
after selectively removing the plurality of portions of the cap layer, bonding a material to the top surface of the interconnect at the discrete locations, wherein the material comprises one of: doped silicon carbide, silicon nitride, and low k material.
12. The method of claim 11 , wherein the predetermined length is a line length below which voids caused by electromigration will not occur.
13. The method of claim 11 , wherein the selectively removing the plurality of portions of the cap layer exposes a plurality of portions of the interconnect, and further comprising cleaning the plurality of portions of the interconnect prior to the bonding the material to the top surface of the interconnect.
14. The method of claim 13 , wherein the cleaning comprises bombarding the plurality of portions of the interconnect with H 2 ions.
15. The method of claim 14 , wherein the cap layer and the material are composed of a same material.
16. A method of forming a semiconductor structure, comprising:
forming an interconnect;
forming a cap on an upper surface of the interconnect, wherein the cap comprises one of: doped silicon carbide, silicon nitride, and low k material;
forming a plurality of electromigration blocks in the cap, wherein each of the plurality of electromigration blocks comprises a hole extending through the cap to the upper surface of the interconnect, and the plurality of electromigration blocks divides the interconnect into segments that are each shorter in length than a predetermined length;
cleaning a plurality of portions of the interconnect that are exposed by the plurality of electromigration blocks in the cap; and
forming an additional cap layer directly on the plurality of portions of the interconnect,
wherein the forming the additional cap layer is performed after the cleaning, and
the additional cap layer comprises a same material as the cap.
17. The method of claim 16 , wherein the interconnect comprises a wide wire having at least one anti-dishing hole, and at least one of the plurality of electromigration blocks coincides with the at least one anti-dishing hole.
18. The method of claim 16 , further comprising:
forming a second interconnect having a second upper surface on which the cap is arranged; and
forming second plurality of electromigration blocks in the cap over the second interconnect,
wherein the second plurality of electromigration blocks are staggered in relation to the plurality of electromigration blocks.