Method and Semiconductor Device Comprising a Protection Layer for Reducing Stress Relaxation in a Dual Stress Liner Approach

1 - 15 . (canceled)

16 . A method, comprising:

forming a tensile-stressed dielectric layer covering a top surface of a gate of an N channel transistor;

forming a dielectric buffer material directly on said tensile-stressed dielectric layer while maintaining the covering of said top surface by said tensile-stressed dielectric layer by performing a spin-coating deposition process without using a plasma ambient, wherein said dielectric buffer material comprises a polymer material;

depositing an interlayer dielectric material above said dielectric buffer material by using a plasma assisted deposition process; and

forming a contact opening in said interlayer dielectric material using said dielectric buffer material as a first etch stop material.

17 .- 19 . (canceled)

20 . A semiconductor device, comprising:

a first transistor formed above a substrate;

a second transistor formed above said substrate;

a first stress-inducing dielectric layer formed above said first transistor and inducing a first type of strain in a channel region of said first transistor;

a second stress-inducing dielectric layer formed above said second transistor and inducing a second type of strain in a channel region of said second transistor;

a polymer material formed above said first and second stress-inducing layers; and

a silicon dioxide based interlayer dielectric material formed above said polymer material.

21 . The semiconductor device of claim 20 , wherein said first transistor is an N-channel transistor and said first stress-inducing layer is a tensile-stressed layer.

22 . The semiconductor device of claim 21 , wherein said second transistor is a P-channel transistor and said second stress-inducing layer is compressive layer.