CMOS TRANSISTORS HAVING DIFFERENTIALLY STRESSED SPACERS
CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.
1 . An n type field effect transistor comprising:
a substrate having a p region,
a first gate dielectric,
a first poly silicon gate electrode having sidewalls over said first gate dielectric,
a tensely stressed spacer on said sidewalls of said first poly silicon gate electrode,
an n type halo region in said p region on opposite sides of said first poly silicon gate electrode,
an n type source and drain extension overlapping said n type halo regions on opposite sides of said first poly silicon gate electrode, and
electrical contacts to said source extension, drain extension and gate electrode.
2 . The n type field effect transistor of claim 1 wherein said tensely stressed spacer is in direct contact to said sidewalls of said first poly silicon gate electrode.
3 . The n type field effect transistor of claim 1 wherein said tensely stressed spacer on said first poly silicon gate electrode is at an interface of said first gate dielectric.
4 . The n type field effect transistor of claim 1 wherein said tensely stressed spacer abuts said halo region.
5 . The n type field effect transistor of claim 1 wherein said tensely stressed spacer is spaced from said sidewalls of said first poly silicon gate electrode by an oxide layer having a thickness in the range from 0.5 to 5 nm.
6 . The n type field effect transistor of claim 1 wherein said first poly silicon gate electrode is selected from the group consisting of SiGe, SiC, Ge, GaAs, combinations thereof and in combination with poly silicon.
7 . A p type field effect transistors comprising:
a substrate having an n region,
a first gate dielectric,
a first poly silicon gate electrode having sidewalls over said first gate dielectric,
a compressively stressed spacer on said sidewalls of said first poly silicon gate electrode,
a p type halo region in said n region on opposite sides of said first poly silicon gate electrode,
a p type source and drain extension overlapping said p type halo regions on opposite sides of said first poly silicon gate electrode, and
electrical contacts to said source extension, drain extension and gate electrode.
8 . The p type field effect transistor of claim 7 wherein said compressively stressed spacer is in direct contact to said sidewalls of said first poly silicon gate electrode.
9 . The p type field effect transistor of claim 7 wherein said compressively stressed spacer on said first poly silicon gate electrode is at an interface of said first gate dielectric.
10 . The p type field effect transistor of claim 7 wherein said compressively stressed spacer abuts said halo region.
11 . The p type field effect transistor of claim 7 wherein said compressively stressed spacer is spaced from said sidewalls of said first poly silicon gate electrode by an oxide layer having a thickness in the range from 0.5 to 5 nm.
12 . The p type field effect transistor of claim 7 wherein said first poly silicon gate electrode is selected from the group consisting of SiGe, SiC, Ge, GaAs, combinations thereof and in combination with poly silicon.
13 . An n type field effect transistor and a p type field effect transistor comprising:
a substrate having p and n regions for forming n and p type field effect transistors respectively therein,
a first gate dielectric and a first poly silicon gate electrode having sidewalls there over on at least one p region,
a second gate dielectric and a second poly silicon gate electrode having sidewalls there over on at least one n region,
a tensely stressed spacer on said sidewalls of said first poly silicon gate electrode, an n type halo region in said p region on opposite sides of said first poly silicon gate electrode,
an n type source and drain extension in said p region overlapping said n type halo regions on opposite sides of said first poly silicon gate electrode,
a compressively stressed spacer on said sidewalls of said second poly silicon gate electrode,
a p type halo region in said n region on opposite sides of said second poly silicon gate electrode, and
a p type source and drain extension in said n region overlapping said p type halo regions on opposite sides of said second poly silicon gate electrode.
14 . The n type field effect transistor and p type field effect transistor of claim 13 wherein said tensely stressed film is positioned directly on exposed sidewalls of said first poly silicon gate electrode.
15 . The n type field effect transistor and p type field effect transistor of claim 13 wherein said tensely stressed film is positioned on said first poly silicon gate electrode at an interface of said first gate dielectric.
16 . The n type field effect transistor and p type field effect transistor of claim 13 wherein said tensely stressed film is positioned on said first poly silicon gate electrode and abutting said p region.
17 . The n type field effect transistor and p type field effect transistor of claim 13 further includes an oxide layer having a thickness in the range from 0.5 to 5 nm on sidewalls of said first poly silicon gate electrode.
18 . The n type field effect transistor and p type field effect transistor of claim 13 wherein said first poly silicon gate electrode is selected from the group consisting of SiGe, SiC, Ge, GaAs, combinations thereof and in combination with poly silicon.
19 . The n type field effect transistor and p type field effect transistor of claim 13 wherein said compressively stressed film is positioned directly on exposed sidewalls of said second poly silicon gate electrode.
20 . The n type field effect transistor and p type field effect transistor of claim 13 wherein said compressively stressed film is positioned on said second poly silicon gate electrode at an interface of said second gate dielectric.
21 . The n type field effect transistor and p type field effect transistor of claim 13 wherein said compressively stressed film is positioned on said second poly silicon gate electrode and abutting said p region.
22 . The n type field effect transistor and p type field effect transistor of claim 13 further including an oxide layer having a thickness in the range from 0.5 to 5 nm on sidewalls of said second poly silicon gate electrode.
23 . The n type field effect transistor and p type field effect transistor of claim 13 wherein said second poly silicon gate electrode is selected from the group consisting of SiGe, SiC, Ge, GaAs, combinations thereof and in combination with poly silicon.
24 . The n type field effect transistor and p type field effect transistor of claim 13 further including:
a dielectric layer positioned over and above said p and n regions including said first and second poly silicon gate electrodes,
said dielectric layer planarized down to said first and second poly silicon gate electrodes, and
contacts contacting said first and second gate electrodes and said source and drain extensions of said n and p type field effect transistors.