Transistor structures and fabrication methods thereof
Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.
1. A structure comprising:
a transistor structure, the transistor structure comprising a first portion and a second portion disposed at least partially within a substrate, the first portion being disposed at least partially between the substrate and the second portion, wherein the first portion inhibits diffusion of material from the second portion into the substrate;
wherein the first portion comprises:
a base portion with a first end and a second end;
a first sidewall coupled to the first end of the base portion at a first end and positioned directly under a spacer of at least one gate structure formed on the substrate at a second end; and
a second sidewall coupled to the second end of the base portion at a first end and positioned directly under a spacer of the at least one gate structure at a second end;
wherein the first sidewall is positioned perpendicular with respect to the base portion and the second sidewall is positioned perpendicular with respect to the base portion;
wherein an exterior surface of the first portion has chamfered edges where the base portion couples to the first sidewall and an exterior surface of the second portion has chamfered edges where the base portion couples to the second sidewall; and
wherein the second end of the first sidewall has a chamfered exterior surface and the second end of the second sidewall has a chamfered exterior surface.
2. The structure of claim 1 , wherein the first portion comprises first impurities and the second portion comprises second impurities, and the first impurities of the first portion inhibit diffusion of the second impurities of the second portion into the substrate.
3. The structure of claim 1 , wherein the first impurities comprise one or more of carbon atoms or fluorine atoms.
4. The structure of claim 1 , wherein the second impurities comprise p-type impurities.
5. The structure of claim 1 , wherein the first portion and the second portion both apply stresses to the substrate.
6. The structure of claim 1 , wherein the first portion and the second portion comprise one semiconductor material, and the substrate comprises another semiconductor material, the one semiconductor material and the another semiconductor material with different lattice constants.
7. The structure of claim 1 , wherein the transistor structure comprises a field-effect transistor structure, and the first portion and the second portion comprise one of a source region or a drain region of the field-effect transistor structure, and the structure further comprises a channel region disposed at least partially within the substrate and adjacent to the one of a source region or a drain region thereof, wherein the first portion inhibits diffusion of the material from the second portion to the channel region.
8. The structure of claim 1 , wherein the transistor structure comprises a bipolar junction transistor structure, the first portion comprising a base region and the second portion comprising an emitter portion thereof, and the structure further comprises a collector region disposed at least partially within the substrate and adjacent to the base thereof, wherein the first portion inhibits diffusion of the material from the second portion to the collector region.
9. The structure of claim 1 , wherein the second portion is spaced from and does not contact the substrate or an isolation region.
10. The structure of claim 1 , wherein a top surface of the first portion of the transistor structure is positioned directly below and in contact with the spacer of at least one gate structure formed on the substrate.
11. The structure of claim 1 , wherein the second portion of the transistor structure is formed directly within the first portion of the transistor structure.