Transistor structures and fabrication methods thereof
Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.
1. A method comprising:
fabricating a transistor structure at least partially within a substrate, the fabricating comprising:
providing a cavity within the substrate; and
forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed between the substrate and the second portion, wherein the second portion is spaced from and does not contact the substrate or an isolation region, and the first portion inhibits diffusion of material from the second portion into the substrate;
wherein the first portion comprises:
a base portion with a first end and a second end;
a first sidewall coupled to the first end of the base portion at a first end and positioned directly under a spacer of at least one gate structure formed on the substrate at a second end; and
a second sidewall coupled to the second end of the base portion at a first end and positioned directly under a spacer of the at least one gate structure at a second end;
wherein the first sidewall is positioned perpendicular with respect to the base and the second sidewall is positioned perpendicular with respect to the base;
wherein the exterior surface of the first portion has chamfered edges where the base couples to the first sidewall and the second sidewall; and
wherein the second end of the first sidewall has a chamfered exterior surface and the second end of the second sidewall has a chamfered exterior surface.
2. The method of claim 1 , wherein the forming comprises using a single epitaxial growth step in forming the first portion and the second portion of the transistor structure.
3. The method of claim 1 , wherein the forming comprises:
providing the first portion with first impurities and the second portion with second impurities, wherein the first impurities of the first portion inhibit diffusion of the second impurities of the second portion into the substrate.
4. The method of claim 3 , wherein the first impurities comprise one or more of carbon atoms or fluorine atoms.
5. The method of claim 3 , wherein the second impurities comprise p-type impurities.
6. The method of claim 3 , wherein the forming comprises:
growing the first portion and the second portion of the transistor structure from a common semiconductor material; and
introducing, during the growing, the first impurities into the first portion and the second impurities into the second portion.
7. The method of claim 1 , wherein the first portion comprises a material selected and configured to inhibit strain relaxation of material of the second portion.
8. The method of claim 1 , wherein the first portion and the second portion both apply stress to the substrate.
9. The method of claim 1 , wherein the first portion and the second portion comprise one semiconductor material, and the substrate comprises another semiconductor material, the one semiconductor material and the another semiconductor material being different semiconductor materials with different lattice constants.
10. The method of claim 1 , wherein the transistor structure comprises a field-effect transistor structure, and the first portion and the second portion comprise one of a source region or a drain region of the field-effect transistor structure, and the fabricating further comprises:
forming a channel region of the field-effect transistor structure at least partially within the substrate and adjacent to the one of a source region or a drain region thereof, wherein the first portion inhibits diffusion of the material from the second portion to the channel region.
11. The method of claim 1 , wherein the transistor structure comprises a bipolar junction transistor structure, the first portion comprising a base region and the second portion comprising an emitter portion thereof, and the fabricating further comprises:
forming a collector region of the bipolar junction transistor structure at least partially within the substrate and adjacent to the base region thereof, wherein the first portion inhibits diffusion of the material from the second portion to the collector region.
12. The method of claim 1 , further comprising:
annealing the transistor structure, wherein the first portion inhibits diffusion of material from the second portion into the substrate notwithstanding the annealing.
13. The method of claim 1 , wherein the second portion of the transistor structure is formed directly within the first portion of the transistor structure.
14. The method of claim 1 , wherein a top surface of the first portion of the transistor structure is positioned directly below and in contact with the spacer of at least one gate structure formed on the substrate.