High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof
View Patent ↗Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.
1. A transistor gate structure, comprising:
a silicon-based substrate comprising nitrogen incorporated proximate a surface of the substrate;
a high-k gate dielectric disposed upon the silicon-based substrate; and
a gate electrode disposed upon the high-k gate dielectric, wherein the gate electrode comprises tantalum nitride rich in tantalum.
2. The transistor gate structure of claim 1 , wherein the nitrogen is present in the silicon-based substrate at a dosage of greater than about 5×10 14 atoms/cm 2 .
3. The transistor gate structure of claim 1 , wherein the high-k gate dielectric comprises hafnium oxide, hafnium silicon oxide, tantalum oxide, aluminum oxide, or a combination comprising at least one of the foregoing dielectrics.
4. The transistor gate structure of claim 1 , wherein the gate structure comprises a Si—N—O layer at an interface between the silicon-based substrate and the high-k gate dielectric for inhibiting the diffusion of oxygen to the substrate.
5. The transistor gate structure of claim 4 , wherein the Si—N—O layer has a thickness of about 0.5 nanometer to about 2 nanometers.
6. The transistor gate structure of claim 1 , wherein the high-k gate dielectric has a thickness of about 1 nanometer to about 5 nanometers.
7. The transistor gate structure of claim 1 , wherein the gate electrode has a thickness of about 1 nanometer to about 20 nanometers.
8. The transistor gate structure of claim 1 , wherein the gate structure has a width of about 0.1 micrometer to about 50 micrometers.