Dual work-function single gate stack
View Patent ↗Disclosed is a complementary CMOS device having a first FET with sidewall channels and a second FET with a planar channel. The first FET can be a p-FET and the second FET can be an n-FET or vice versa. The conductor used to form the gate electrodes of the different type FETs is different and is pre-selected to optimize performance. For example, a p-FET gate electrode material can have a work function near the valence band and an n-FET gate electrode material can have a work function near the conduction band. The first gate electrodes of the first FET are located adjacent to the sidewall channels and the second gate electrode of the second FET is located above the planar channel. However, the device structure is unique in that the second gate electrode extends laterally above the first FET and is electrically coupled to the first gate electrodes.
1. A method of forming a complementary metal oxide semiconductor (CMOS) device, comprising:
providing a wafer comprising a substrate, an isolation layer on said substrate, and a semiconductor layer on said isolation layer;
etching said wafer through said semiconductor layer in order to form at least one first semiconductor body for an n-type field effect transistor and a second semiconductor body for a p-type field effect transistor;
forming first gate electrodes adjacent to sidewalls of said at least one first semiconductor body, wherein said first gate electrodes are formed with a first conductive material; and
forming a second gate electrode adjacent to a top surface of said second semiconductor body such that said second gate electrode extends laterally above said at least one first semiconductor body and is electrically coupled to said first gate electrodes, wherein said second gate electrode is formed with a second conductive material that is different from said first conductive material.
2. The method of forming a CMOS device according to claim 1 , wherein said forming of said first gate electrodes with said first conductive material comprises forming said first gate electrodes with one of a conduction band metal and an n-doped polysilicon and wherein said forming of said second gate electrode with said second conductive material comprises forming said second gate electrode with one of a valence band metal and a p-doped polysilicon.
3. The method of forming a CMOS device according to claim 1 , further comprising, before said forming of said second gate electrode, forming metal silicide regions on top of said first gate electrodes.
4. The method of forming a CMOS device according to claim 1 , wherein said forming of said first gate electrodes comprises:
depositing a dielectric layer;
forming a recess in said dielectric layer such that said sidewalls of said at least one first semiconductor bodies are exposed at a center region; and
depositing said first conductive material into said recess.
5. The method of forming a CMOS device according to claim 1 , wherein said forming of said first gate electrodes comprises forming, adjacent to said sidewalls at a center region of said at least one first semiconductor bodies, sidewall spacers comprising said first conductive material.
6. A method of forming a complementary metal oxide semiconductor (CMOS) device, comprising:
providing a wafer comprising a substrate, an isolation layer on said substrate, and a semiconductor layer on said isolation layer;
etching said wafer through said semiconductor layer in order to form at least one first semiconductor body for a p-type field effect transistor and a second semiconductor body for an n-type field effect transistor;
forming first gate electrodes adjacent to sidewalls of said at least one first semiconductor body, wherein said first gate electrodes are formed with a first conductive material; and
forming a second gate electrode adjacent to a top surface of said second semiconductor body such that said second gate electrode extends laterally above said at least one first semiconductor body and is electrically coupled to said first gate electrodes, wherein said second gate electrode is formed with a second conductive material that is different from said first conductive material.
7. The method of forming a CMOS device according to claim 6 , wherein said forming of said first gate electrode with said first conductive material comprises forming said first gate electrodes with one of a valence band metal and a p-doped polysilicon and wherein said forming of said second gate electrode with said second conductive material comprises forming said second gate electrode with one of a conduction band metal and an n-doped polysilicon.
8. The method of forming a CMOS device according to claim 6 , further comprising, before said forming of said second gate electrode, forming metal silicide regions on top of said first gate electrodes.
9. The method of forming a CMOS device according to claim 6 , wherein said forming of said first gate electrodes comprises:
depositing a dielectric layer;
forming a recess in said dielectric layer such that said sidewalls of said at least one first semiconductor bodies are exposed at a center region; and
depositing said first conductive material into said recess.
10. The method of forming a CMOS device according to claim 6 , wherein said forming of said first gate electrodes comprises forming, adjacent to said sidewalls at a center region of said at least one first semiconductor bodies, sidewall spacers comprising said first conductive material.
11. A method of forming a complementary metal oxide semiconductor (CMOS) device, comprising:
providing a wafer comprising a substrate, an isolation layer on said substrate, and a semiconductor layer on said isolation layer;
etching said wafer through said semiconductor layer in order to form at least one first semiconductor body for an n-type field effect transistor and a second semiconductor body for a p-type field effect transistor;
forming first gate electrodes adjacent to sidewalls of said at least one first semiconductor body, wherein said first gate electrodes are formed with a first conductive material;
forming a second gate electrode adjacent to a top surface of said second semiconductor body such that said second gate electrode extends laterally above said at least one first semiconductor body and is electrically coupled to said first gate electrodes, wherein said second gate electrode is formed with a second conductive material that is different from said first conductive material; and
forming an isolation region on said insulator layer positioned between a first gate electrode of said n-type field effect transistor and a second opposing sidewall of said p-type field effect transistor.
12. The method of forming a CMOS device according to claim 11 , wherein said forming of said first gate electrodes with said first conductive material comprises forming said first gate electrodes with one of a conduction band metal and an n-doped polysilicon and wherein said forming of said second gate electrode with said second conductive material comprises forming said second gate electrode with one of a valence band metal and a p-doped polysilicon.
13. The method of forming a CMOS device according to claim 11 , further comprising, before said forming of said second gate electrode, forming metal silicide regions on top of said first gate electrodes.
14. The method of forming a CMOS device according to claim 11 , wherein said forming of said first gate electrodes comprises:
depositing a dielectric layer;
forming a recess in said dielectric layer such that said sidewalls of said at least one first semiconductor bodies are exposed at a center region; and
depositing said first conductive material into said recess.
15. The method of forming a CMOS device according to claim 11 , wherein said forming of said first gate electrodes comprises forming, adjacent to said sidewalls at a center region of said at least one first semiconductor bodies, sidewall spacers comprising said first conductive material.