Methods for fabricating non-planar semiconductor devices having stress memory
Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer.
1. A method for fabricating a semiconductor device including a substrate, an N-type non-planar transistor having a first plurality of fin structures, and a P-type non-planar transistor having a second plurality of fin structures, the method comprising the steps of:
selectively amorphorizing a portion of each fin structure included within the first plurality of fin structures utilizing at least a first angled ion implantation process;
depositing a first sacrificial strain layer over the first plurality of fin structures to apply stress to the amorphized portions thereof;
annealing the non-planar semiconductor device to recrystallize the amorphized portion of each fin structure included within the first plurality of fin structures in a stress-memorized state;
removing the first sacrificial strain layer;
selectively amorphorizing a portion of each fin structure included within the second plurality of fin structures utilizing at least a second angled ion implantation process;
depositing a second sacrificial strain layer over the second plurality of fin structures to apply stress to the amorphized portions thereof;
annealing the non-planar semiconductor device to recrystallize the amorphized portion of each fin structure included within the second plurality of fin structures in a stress-memorized state;
removing the second sacrificial strain layer; and
forming a plurality of gate stacks overlying the first and second pluralities of raised crystalline structures, the step of forming a plurality of gate stacks performed after the steps of annealing.
2. A method according to claim 1 wherein the step of depositing a first sacrificial strain layer comprises blanket depositing a first type of strain material over the semiconductor device, and wherein the step of depositing a second sacrificial strain layer comprises blanket depositing a second type of strain material over the semiconductor device, the second type of strain material different from the first type of strain material.
3. A method according to claim 2 wherein the first type of strain material and the second type of strain material are each selected from the group consisting of tensile nitride and compressive nitride.
4. A method according to claim 1 wherein the step of selectively amorphorizing comprises:
positioning a mask over the second plurality of fin structures; and
bombarding the first plurality of tin structures with an electrically neutral amorphorizing species from a first predetermined direction forming an acute grazing angle with the substrate.