MOSFET WITH LATERALLY GRADED CHANNEL REGION AND METHOD FOR MANUFACTURING SAME
The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along a direction that is substantially parallel to a substrate surface in which the semiconductor device is located. Specifically, the semiconductor device comprises a field effect transistor (FET) that has a SiGe channel with a laterally graded germanium content.
1 . A semiconductor device, comprising:
a semiconductor substrate having a substrate surface;
a source region located in the substrate surface;
a drain region located in the substrate surface and spaced apart from the source region;
a channel region located in the substrate surface between the source and drain region; and
a gate structure located over the channel region, said gate structure comprising a gate dielectric layer and a gate electrode,
wherein the channel region comprises a semiconductor alloy comprising a first material and a second, different material, and wherein concentration of the second material in the channel region is graded along a direction that is substantially parallel to said substrate surface.
2 . The semiconductor device of claim 1 , wherein the semiconductor substrate comprises a semiconductor-on-insulator structure.
3 . The semiconductor device of claim 1 , wherein the semiconductor substrate comprises a bulk semiconductor structure.
4 . The semiconductor device of claim 1 , wherein the channel region is doped with an n-type dopant.
5 . The semiconductor device of claim 1 , wherein the channel region is doped with a p-type dopant.
6 . The semiconductor device of claim 1 , wherein the source, drain, and channel regions define a current flow direction that is substantially parallel to the substrate surface, and wherein the concentration of the second material in the channel region is graded along the current flow direction.
7 . The semiconductor device of claim 1 , wherein the first and second materials are selected from the group consisting of Si, Ge, C, Ga, As, In, Al, Sb, B, Pb, and combinations thereof.
8 . The semiconductor device of claim 1 , wherein the first material is silicon, and the second material is germanium.
9 . The semiconductor device of claim 1 , wherein the channel region has a channel length ranging from about 10 nm to about 100 nm.
10 . The semiconductor device of claim 9 , wherein the concentration of the second material in the channel region is graded from an initial concentration ranging from about 0 atomic % to about 10 atomic % to a final concentration ranging from about 15 atomic % to about 100 atomic %, or from an initial concentration of from about 15 atomic % to about 100 atomic % to a final concentration of from about 0 atomic % to about 11 atomic %.
11 . The semiconductor device of claim 9 , wherein the gate electrode is substantially aligned with the channel region along a direction perpendicular to the surface of the semiconductor substrate.
12 . The semiconductor device of claim 1 , wherein the channel region and at least one of the source and drain regions comprise semiconductor material layers that are epitaxially grown along a growth direction that is substantially parallel to the surface of the semiconductor substrate.