Raised source/drain field effect transistor

1. A semiconductor structure comprising:

a substrate having a surface; and

a plurality of gate structure devices at least partially overlying the substrate, where the plurality of gate structure devices comprises a first gate structure device and a second gate structure device defining a gate-to-gate spacing therebetween, the first gate structure device coupled to the second gate structure device via a first raised source/drain formed in a gate-to-gate source/drain area defined by the gate-to-gate spacing and having a first length determined by a minimum gate-to-gate source/drain area operable to minimize parasitic capacitance associated with the first gate structure device and the second gate structure device and having a first height, where the first gate structure device is further coupled to a second raised source/drain having a second length and a second height, where the first gate structure device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overlie the surface of the substrate by said first height and said second height, respectively, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length so that the second raised source/drain having the relatively greater second length is effective for providing the terminal electrical contact, and the second height is greater than the first height, where the first raised source/drain and the second raised source/drain comprise a faceted epitaxy structure having a generally triangle-shaped cross section, and the faceted epitaxy structure of the second raised source/drain is larger than the faceted epitaxy structure of the first raised source/drain.

2. The semiconductor structure of claim 1 , where the first gate structure device comprises a field effect transistor.

3. The semiconductor structure of claim 1 , where the second gate structure device comprises a second transistor, a second field effect transistor, a passive device, a capacitor or a resistor.

4. The semiconductor structure of claim 1 , where the second gate structure device is further coupled to a third gate structure device via a third raised source/drain having a third length, where the second length is greater than the third length.

5. The semiconductor structure of claim 1 , where the first length is about 15 nm and the second length is about 30 nm.

6. The semiconductor structure of claim 1 , where at least one of the first raised source/drain and the second raised source/drain comprises a generally triangular cross-section.

7. The semiconductor structure of claim 1 , where the first raised source/drain is not operable to connect to a further device or component.

8. The semiconductor structure of claim 1 , where the gate-to-gate spacing for at least two devices of the plurality of devices is less than a length of at least one contact area on the semiconductor structure.

9. The semiconductor structure of claim 1 , where the semiconductor structure comprises a NAND gate.

10. The semiconductor structure of claim 1 , where the substrate comprises a silicon-on-insulator, a thin silicon-on-insulator, a partially depleted silicon-on-insulator, a fully depleted silicon-on-insulator or a bulk substrate.

11. The semiconductor structure of claim 1 , where at least one of the first raised source/drain and the second raised source/drain has a trapezoidal cross-section.

12. A semiconductor structure, comprising:

a substrate having a surface; and

a plurality of gate structure devices at least partially overlying the substrate, where the plurality of gate structure devices comprises a first gate structure device and a second gate structure device defining a gate-to-gate spacing therebetween, where the first gate structure device comprises a transistor; and

a first raised source/drain in a gate-to-gate source/drain area defined by the gate-to-gate spacing and a second raised source/drain, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the first gate-structure device is connected to the second gate structure device via the first raised source/drain, where the first gate structure device is further coupled to the second raised source/drain, where the first raised source/drain has a first length and the second raised source/drain has a second length, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length so that the second raised source/drain having the relatively greater second length is effective for providing the terminal electrical contact, where the first raised source/drain and the second raised source/drain comprise a faceted epitaxy having a generally triangle-shaped cross section, and the faceted epitaxy structure of the second raised source/drain is larger than the faceted epitaxy structure of the first raised source/drain.

13. The semiconductor structure of claim 12 , further comprising: silicide formed over at least the second raised source/drain.

14. The semiconductor structure of claim 12 , further comprising: a double spacer formed around the first gate structure device.

15. The semiconductor structure of claim 12 , further comprising: a contact formed at the second raised source/drain.

16. The semiconductor structure of claim 12 , where the first length is on the order of 15 nm and the second length is on the order of 30 nm.

17. The semiconductor structure of claim 12 , where the ratio of the second length to the first length is substantially 2:1.