REDUCING THE CREATION OF CHARGE TRAPS AT GATE DIELECTRICS IN MOS TRANSISTORS BY PERFORMING A HYDROGEN TREATMENT
By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors.
1 . A method, comprising:
performing at least one heat treatment in a hydrogen-containing ambient on a substrate having formed thereon an exposed silicon-containing semiconductor surface;
forming a gate dielectric material on said silicon-containing semiconductor surface; and
forming a field effect transistor on the basis of said gate dielectric material.
2 . The method of claim 1 , further comprising forming a trench isolation structure in a silicon-containing semiconductor layer including said surface by patterning a trench and refilling said trench with a dielectric material.
3 . The method of claim 2 , wherein said at least one heat treatment in a hydrogen-containing ambient is performed prior to patterning said trench, when said silicon-containing semiconductor surface is in an exposed state.
4 . The method of claim 2 , further comprising introducing dopant species into said silicon-containing semiconductor layer using a pad material, wherein said at least one heat treatment in a hydrogen-containing ambient is performed prior to forming said pad material.
5 . The method of claim 1 , wherein forming said gate dielectric material comprises forming a first gate dielectric layer at first locations and forming a second gate dielectric layer at second locations on said silicon-containing semiconductor surface, said first gate dielectric layer having a first thickness that is other than a second thickness of said second gate dielectric layer.
6 . The method of claim 5 , wherein said at least one heat treatment in a hydrogen-containing ambient is performed prior to forming said first gate dielectric layer and after forming a trench isolation structure in said silicon-containing semiconductor layer.
7 . The method of claim 5 , wherein said at least one heat treatment in a hydrogen-containing ambient is performed prior to forming said second gate dielectric layer and after forming said first gate dielectric layer.
8 . The method of claim 5 , wherein said at least one heat treatment in a hydrogen-containing ambient is performed prior to forming said first gate dielectric layer and one further heat treatment in a hydrogen-containing ambient is performed prior to forming said second gate dielectric layer.
9 . The method of claim 1 , wherein two or more heat treatments in a hydrogen-containing ambient are performed in respective different manufacturing stages prior to forming said gate dielectric material, wherein said silicon-containing semiconductor surface is in an exposed state in each of said respective different manufacturing stages.
10 . The method of claim 8 , wherein three or more heat treatments in a hydrogen-containing ambient are performed in respective different manufacturing stages prior to forming said gate dielectric material, wherein said silicon-containing semiconductor surface is in an exposed state in each of said respective different manufacturing stages.
11 . The method of claim 1 , wherein said hydrogen-containing ambient is a hydrogen ambient.
12 . A method of forming a gate dielectric material, the method comprising:
performing a first heat treatment on an exposed silicon-containing semiconductor surface in the presence of hydrogen; and
forming a first gate insulation layer on said exposed silicon-containing semiconductor surface.
13 . The method of claim 12 , further comprising creating a dopant profile in a silicon-containing semiconductor layer including said surface and performing said first heat treatment after creating said dopant profile.
14 . The method of claim 12 , further comprising forming a trench isolation structure in a silicon-containing layer including said surface prior to forming said first gate insulation layer, wherein said first heat treatment is performed prior to forming said trench isolation structure.
15 . The method of claim 12 , further comprising forming a second gate insulation layer on said silicon-containing semiconductor surface, said second gate insulation layer having a thickness differing from a thickness of said first gate insulation layer.
16 . The method of claim 15 , wherein said first heat treatment is performed prior to forming said second gate insulation layer and after forming said first gate insulation layer.
17 . The method of claim 15 , wherein said first heat treatment is performed prior to forming said first gate insulation layer, and wherein the method further comprises performing a second heat treatment in the presence of hydrogen after forming said first gate insulation layer and prior to forming said second gate insulation layer.
18 . The method of claim 14 , further comprising performing a second heat treatment in the presence of hydrogen after performing said first heat treatment and prior to forming said first gate insulation layer.
19 . The method of claim 18 , further comprising performing a third heat treatment in the presence of hydrogen prior to forming said first gate insulation layer.
20 . A method, comprising:
determining, in a manufacturing flow for forming a gate dielectric material of a transistor, a state with an exposed silicon surface of a silicon layer of a semiconductor device;
exposing a substrate comprising said silicon layer at least once to a hydrogen ambient, said hydrogen ambient interacting with a surface of said silicon layer; and
forming a gate insulation layer on said silicon layer after interacting with said hydrogen ambient.
21 . The method of claim 20 , wherein said substrate is exposed two or more times to said hydrogen ambient.
22 . The method of claim 21 , wherein said substrate is exposed to said hydrogen ambient at each determined state with an exposed silicon surface prior to forming said gate insulation layer.