Raised Source/Drain Field Effect Transistor
In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length.
1 . A method comprising:
forming a plurality of devices at least partially overlying a substrate, where the plurality of devices comprises a first device and a second device, where the first device comprises a transistor; and
forming a first raised source/drain and a second raised source/drain, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the first device is connected to the second device via the first raised source/drain, where the first device is further coupled to the second raised source/drain, where the first raised source/drain has a first length and the second raised source/drain has a second length, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length.
2 . The method of claim 1 , where forming the first raised source/drain and the second raised source/drain comprises performing a faceted epitaxy to deposit material.
3 . The method of claim 1 , further comprising: forming silicide over at least the second raised source/drain.
4 . The method of claim 1 , further comprising: forming a double spacer around the first device.
5 . The method of claim 1 , further comprising: forming a contact at the second raised source/drain.