USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES
Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.
1 . A method of creating differential stress in a plurality of contacts in an integrated circuit (IC) chip, the method comprising:
providing a substrate including a p-type field effect transistor (PFET) and a n-type field effect transistor (NFET), the PFET and NFET each including a source/drain region;
forming a silicide layer over the PFET and the NFET;
depositing at least one nitride layer over the substrate;
depositing a dielectric layer over the at least one nitride layer;
etching a PFET contact trench through the dielectric layer down to the at least one nitride layer on the PFET;
etching an NFET contact trench through the dielectric layer down to the at least one nitride layer on the NFET;
opening the at least one nitride layer in a selected contact trench of a selected FET of the PFET and the NFET;
etching the selected contact trench through the silicide layer into the source/drain region of the selected FET, and opening the at least one nitride layer on the FET that is not the selected FET;
filling the PFET contact trench to form a PFET contact; and
filling the NFET contact trench to form an NFET contact,
wherein in the case that the PFET is the selected FET, the PFET contact extends into the source/drain region of the PFET, and in the case that the NFET is the selected FET, the NFET contact extends into the source/drain region of the NFET.
2 . The method of claim 1 , wherein in the case that the PFET contact extends into the PFET, the PFET contact comprises one of the following materials: nickel (Ni), platinum (Pt), palladium (Pd), titanium (Ti) or cobalt (Co).
3 . The method of claim 1 , wherein in the case that the PFET contact extends into the PFET, the PFET contact includes a silicide reaction layer between the PFET contact and the source/drain region of the PFET.
4 . The method of claim 1 , wherein in the case that the NFET contact protrudes into the NFET, the NFET contact comprises one of the following materials: tungsten (W), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN) or copper (Cu).
5 . The method of claim 1 , wherein in the case that the PFET contact extends into the PFET, the PFET contact extends approximately 50 to approximately 3000 angstroms into the source/drain region of the PFET, and wherein in the case that the NFET contact extends into the NFET, the NFET contact extends approximately 50 to 3000 angstroms into the source/drain region of the NFET.