Serial interface having a read temperature command
View Patent ↗A serial communication system includes an integrated circuit having a master serial interface; and a processor having a slave serial interface coupled to the master serial interface through a clock signal line and a data signal line. The slave serial interface is responsive to a read temperature command issued by the master serial interface to return a first temperature value associated with the processor.
1. A serial communication system comprising:
an integrated circuit having a master serial interface; and
a processor having a slave serial interface coupled to the master serial interface through a clock signal line and a data signal line wherein the slave serial interface is responsive to a read temperature command issued by the master serial interface to return a temperature value associated with the processor.
2. The serial communication system as recited in claim 1 wherein the temperature value is returned as a sixteen bit value having a most significant and a least significant byte, and wherein the most significant byte returned represents an integer portion of the temperature value from 0° to 255° C. and wherein the upper three bits of the least significant byte returned represents a fractional portion of the temperature value from 0° C. to 0.875° C. in increments equal to 0.125° C.
3. The serial communication system as recited in claim 1 wherein the slave serial interface is responsive to at least one additional read temperature command to return at least one additional temperature value associated with the processor.
4. The serial communication system as recited in 3 wherein the temperature value includes one or more offsets to a measured temperature.
5. The serial communication system as recited in claim 1 wherein protocol on the serial communication system includes, an initialization condition where the master serial interface drives at least 32 consecutive clock cycles of 1's on the data line to the slave serial interface, a start condition wherein the master serial interface signals a start condition by driving the data line low for one clock cycle of the clock signal line following the initialization condition, a command phase, and a data phase.
6. The serial communication system as recited in claim 5 wherein a last bit of the data phase for a read temperature command includes a valid bit, the valid bit being at a first value to indicate that the data is valid and at a second value to indicate that the slave serial interface is not ready.
7. The serial communication system as recited in claim 1 wherein the slave serial interface is further responsive to a read node ID command to return an identification associated with the processor.
8. A method for communicating over a point to point serial communication system having a clock signal line and a data signal line coupling a serial interface master and a serial interface slave, the method comprising:
sending a read temperature command to the serial interface slave from the serial interface master using the clock signal line and the data signal line; and
in response to the read temperature command, the serial interface slave supplying over the data signal line a temperature value associated with a processor on an integrated circuit containing the serial interface slave.
9. The method as recited in claim 8 wherein the temperature value is returned as a fixed point number.
10. The method as recited in claim 8 further comprising the serial interface slave responding to another read temperature command from the serial interface master to return another temperature value associated with the processor.
11. The method as recited in claim 8 wherein protocol on the serial communication system includes an initialization condition where the serial interface master drives at least 32 consecutive clock cycles of 1's on the data line to the serial interface slave, a start condition wherein the serial interface master signals a start condition by driving the data line low for one clock cycle of the clock signal line following the initialization condition, a command phase, and a data phase.
12. The method as recited in claim 11 further comprising the serial interface slave sending as a last bit of the data phase for a read temperature command a valid bit, the valid bit being at a first value to indicate that the data is valid and at a second value to indicate that the serial interface slave is not ready.
13. The method as recited in claim 11 further comprising the serial interface slave responding to a read node ID command to return an identification associated with the processor over the data line.
14. A serial communication system comprising:
a microprocessor having a slave serial interface for coupling to a master serial interface through a clock signal line output terminal and a data signal line output terminal wherein the slave serial interface is responsive to a read temperature command issued by the master serial interface to return to the master serial interface a temperature value associated with the microprocessor.
15. The serial communication system as recited in claim 14 further comprising an integrated circuit incorporating the master serial interface coupled to the clock signal line output terminal and a data signal line output terminal via a clock signal line and a data signal line coupled to the master serial interface.
16. The serial communication system as recited in claim 15 wherein the slave serial interface is responsive to another read temperature command, the other read temperature command having a different decode value than the read temperature command, to return another temperature value associated with the microprocessor.
17. The serial communication system as recited in claim 15 wherein protocol on the serial communication system includes an initialization condition where the master serial interface drives at least 32 consecutive clock cycles of 1's on the data line to the slave serial interface, a start condition wherein the master serial interface signals a start condition by driving the data line low for one clock cycle of the clock signal line following the initialization condition, a command phase, and a data phase.
18. The serial communication system as recited in claim 17 wherein a last bit of the data phase for the read temperature command includes a valid bit, the valid bit being at a first value to indicate that the data is valid and at a second value to indicate that the slave serial interface is not ready.
19. The serial communication system as recited in claim 15 wherein the slave serial interface is further responsive to a read node ID command to return an identification associated with the microprocessor.
20. The serial communication system as recited in claim 19 wherein the slave serial interface is further responsive to a version command to return an identification of a version of the serial communication system supported by the microprocessor.