Patent Assignment
Reel/Frame 055173/0781
Assignment of Assignor's Interest
Recorded: 2021-01-29
Pages: 15
Assignor
GLOBALFOUNDRIES US INC.
Executed: 2020-12-23
Assignee
MEDIATEK INC.
NO. 1, DUSING 1ST RD. , HSINCHU SCIENCE PARK, HSINCHU CITY, 30078, TAIWAN
Covered Properties
(162)
Arrangement in a Network Repeater for Monitoring Link Integrity and Automatically Down Shifting Link Speed
Patent:
8,184,677 →
Application:
09/256,786 →
Method and Apparatus for Powering Down the Cpu/Memory Controller Complex While Preserving the Self Refresh State of Memory in the System
Patent:
7,039,755 →
Application:
09/584,301 →
A System and Method for Selecting Between a Voltage Specified by a Processor and an Alternate Voltage to Be Supplied to He Processor
Patent:
6,748,545 →
Application:
09/621,931 →
Method and Interface for Glitch-Free Clock Switching
Method and System of Automatic Delay Detection and Receiver Adjustment for Synchronous Bus Interface
Method and Apparatus for Securing Portions of Memory
Secure Execution Box
Patent:
7,065,654 →
Application:
09/852,372 →
Interruptable and Re-Enterable System Management Mode Programming Code
Patent:
6,862,641 →
Application:
09/853,234 →
Enhanced Security and Manageability Using Secure Storage in a Personal Computer System
Patent:
7,216,362 →
Application:
09/853,395 →
Personal Computer Security Mechansim
Patent:
6,832,317 →
Application:
09/853,437 →
Integrated Circuit for Security and Manageability
Patent:
6,823,451 →
Application:
09/853,447 →
Using Type Bits to Track Storage of Ecc and Predecode Bits in a Level Two Cache
Software Modem for Communicating Data Using Encrypted Data and Unencrypted Control Codes
Harmonic Mixer
Patent:
7,085,548 →
Application:
09/904,751 →
Power State Resynchronization
Patent:
6,795,927 →
Application:
09/907,083 →
Apparatus and Method for Providing an External Clock from a Circuit in Sleep Mode in a Processor -Based System
Patent:
6,832,327 →
Application:
09/969,304 →
Processing Tasks with Failure Recovery
Patent:
7,305,675 →
Application:
10/044,707 →
Computer Graphics Processing System, Computer Memory, and Method of Use with Computer Graphics Processing System Utilizing Hierarchical Image Depth Buffer
Patent:
7,030,877 →
Application:
10/090,507 →
Computer System Initialization via Boot Code Stored in a Non-Volatile Memory Having an Interface Compatible with Synchronous Dynamic Random Access Memory
Patent:
7,058,779 →
Application:
10/091,766 →
Input/Output Permission Bitmaps for Compartmentalized Security
Patent:
7,493,498 →
Application:
10/107,784 →
System and Method Providing Region-Granular, Hardware-Controlled Memory Encryption
Piggybacking of Ecc Corrections Behind Loads
Patent:
7,043,679 →
Application:
10/180,207 →
Ata and Sata Compliant Controller
High Speed Clock Divider with Synchronous Phase Start-Up Over Physically Distributed Space
Computer System with Processor Cache That Stores Remote Cache Presence Information
Patent:
7,096,323 →
Application:
10/256,970 →
On-Chip High Speed Data Interface
Digital Automatic Gain Control for Transceiver Devices
Ata/Sata Combined Controller
Direct Conversion Receiver Having a Gain-Setting Dependent Filter Parameter
Retry Mechanism for Blocking Interfaces
Parallel fault detection
System and Method for State-Based Profiling of Multiprocessor Systems
Patent:
7,305,663 →
Application:
10/323,987 →
Passive Impedance Network for Rotating a Phase System
Extended Host Controller Test Mode Support for Use with Full-Speed Usb Devices
Electronic Circuit with Improved Current Stabilisation
Equalizing Circuit with Notch Compensation for a Direct Coversion Receiver
Method for Selectively Disabling Interrupts on a Secure Execution Mode-Capable Processor
Patent:
7,130,951 →
Application:
10/419,091 →
System and Method for Facilitating Communication Across an Asynchronous Clock Boundary
Patent:
7,035,983 →
Application:
10/423,993 →
Ddr on-the-Fly Synchronization
Patent:
7,177,379 →
Application:
10/425,974 →
System and Method for Blocking Cache Use During Debugging
Patent:
7,055,006 →
Application:
10/426,755 →
Speculation Pointers to Identify Data-Speculative Operations in Microprocessor
Apparatus and Method for Balanced Spinlock Support in Numa Systems
Patent:
7,334,102 →
Application:
10/434,692 →
Non-Abrupt Switching of Sleep Transistor of Power Gate Structure
System and Method of Implementing Microcode Operations as Subroutines
Patent:
7,694,110 →
Application:
10/614,970 →
Circular Buffer Using Grouping for Find First Function
Patent:
6,873,184 →
Application:
10/653,802 →
System and Method for Handling Exceptional Instructions in a Trace Cache Based Processor
Facilitating Cold Reset and Warm Reset Tasking in a Computer System
Patent:
7,165,172 →
Application:
10/676,600 →
Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming
Patent:
7,043,626 →
Application:
10/676,636 →
Latch Circuit with Metastability Trap and Method Therefor
Patent:
6,924,682 →
Application:
10/683,823 →
Frequency Domain Estimation of Iq Imbalance in a Wireless Ofdm Direct Conversion Receiver Using Loopback Connection
Patent:
7,184,714 →
Application:
10/699,667 →
Autonomous Self-Monitoring and Corrective Operation of an Integrated Circuit
Single Supply Level Converter
Transitioning from Instruction Cache to Trace Cache on Label Boundaries
Controlling Writes to Non-Renamed Register Space in an Out-of-Order Execution Microprocessor
Patent:
7,373,484 →
Application:
10/755,692 →
Ofdm Receiver Having Adaptive Channel Estimator for Correcting Channel Fading Based on Accumulated Pseudo Power Values
Patent:
7,356,108 →
Application:
10/817,811 →
Network Interface with Security Association Data Prefetch for High Speed Offloaded Security Processing
Media Accelerator Interface Api
Patent:
7,725,905 →
Application:
10/843,255 →
Method for Optimizing Loop Control of Microcoded Instructions
Patent:
7,366,885 →
Application:
10/858,791 →
Data Processor Having a Cache with Efficient Storage of Predecode Information, Cache, and Method
Patent:
7,827,355 →
Application:
10/887,069 →
Method and Apparatus for Dynamic Adjustment of a Sensor Sampling Rate
Patent:
7,558,687 →
Application:
10/932,999 →
Combined System Responses in a Chip Multiprocessor
Patent:
7,296,167 →
Application:
10/956,537 →
Dynamic Reconfiguration of Cache Memory
Digitally Controlled Filter Tuning for Wlan Communication Devices
Dual-Mode Output Driver Configured for Outputting a Signal According to Either a Selected High Voltage/Low Speed Mode or a Low Voltage/High Speed Mode
Patent:
7,154,309 →
Application:
11/033,754 →
Alignment of Local Transmit Clock to Synchronous Data Transfer Clock Having Programmable Transfer Rate
Patent:
7,256,627 →
Application:
11/033,755 →
Voltage Mode Transceiver Having Programmable Voltage Swing and External Reference-Based Calibration
Patent:
7,135,884 →
Application:
11/033,757 →
Scratch Pad for Storing Intermediate Loop Filter Data
Executing System Management Mode Code as Virtual Machine Guest
Patent:
7,418,584 →
Application:
11/066,752 →
Virtualization of Real Mode Execution
Patent:
8,127,098 →
Application:
11/066,873 →
System for Enabling and Disabling Cache and a Method Thereof
Patent:
7,694,075 →
Application:
11/076,323 →
System for Speculative Branch Prediction Optimization and Method Thereof
System and method for aligning change-of-flow instructions in an instruction buffer
Patent:
8,578,134 →
Application:
11/098,273 →
Serial Interface Having a Read Temperature Command
Patent:
7,231,474 →
Application:
11/140,803 →
Microprocessor Including a Configurable Translation Lookaside Buffer
Control of Pci Memory Read Behavior Using Memory Read Alias and Memory Command Reissue Bits
Patent:
7,657,690 →
Application:
11/151,318 →
Using a Shuffle Unit to Implement Shift Operations in a Processor
Patent:
7,464,255 →
Application:
11/192,153 →
Verified Computing Environment for Personal Internet Communicator
Time Weighted Moving Average Filter
Computer Graphics Processing System, Computer Memory, and Method of Use with Computer Graphics Processing System Utilizing Hierarchical Image Depth Buffer
Patent:
7,315,301 →
Application:
11/279,981 →
Delay-Locked Loop Having a Plurality of Lock Modes
Patent:
7,271,634 →
Application:
11/286,454 →
Memory Access Request Arbitration
Secure Patch Installation for Wwan Systems
Strided Block Transfer Instruction
Patent:
8,432,409 →
Application:
11/317,593 →
Data Block Transfer to Cache
Patent:
8,368,710 →
Application:
11/321,706 →
System and Method for Operating Components of an Integrated Circuit at Independent Frequencies and/or Voltages
Method and Apparatus for Crosstalk Reduction
Patent:
7,561,625 →
Application:
11/348,136 →
Asymmetric Control of High-Speed Bidirectional Signaling
System for Phase Tracking and Equalization Across a Byte Group for Asymmetric Control of High-Speed Bidirectional Signaling
Patent:
7,506,222 →
Application:
11/368,792 →
Error Detection in a Communication Link
Patent:
7,596,742 →
Application:
11/379,864 →
Incrementally Adjustable Skew and Duty Cycle Correction for Clock Signals Within a Clock Distribution Network
Patent:
7,765,425 →
Application:
11/385,329 →
Controlling an I/O Mmu
System and Method for Limiting Processor Performance
System for Controlling High-Speed Bidirectional Communication
Cml Delay Cell with Linear Rail-to-Rail Tuning Range and Constant Output Swing
Digital Measuring System and Method for Integrated Circuit Chip Operating Parameters
Filtering and Remapping Interrupts
Memory Controller Including a Dual-Mode Memory Interconnect
Memory System Including Asymmetric High-Speed Differential Memory Interconnect
Partial Crc Insertion in Data Packets for Early Forwarding
Address Translation for Input/Output (I/O) Devices and Interrupt Remapping for I/O Devices in an I/O Memory Management Unit (Iommu)
Redirect Recovery Cache That Receives Branch Misprediction Redirects and Caches Instructions to Be Dispatched in Response to the Redirects
Over Temperature Detection Apparatus and Method Thereof
Branch Predictor Directed Prefetch
Parallel Instruction Processing and Operand Integrity Verification
Phase Select Circuit with Reduced Hysteresis Effect
Technique for Prefetching Data Based on a Stride Pattern
Method and Apparatus for Length Decoding Variable Length Instructions
Method and Apparatus for Length Decoding and Identifying Boundaries of Variable Length Instructions
Level Shifter Circuit with Pre-Charge/Pre-Discharge
Method and Apparatus for Clock Cycle Stealing
System and Method for Controlling Video Inputs to a Computer
Time Stamping Transactions to Validate Atomic Operations in Multiprocessor Systems
Processing Tasks with Failure Recovery
Mechanism to Accelerate Removal of Store Operations from a Queue
Processing Pipeline Having Parallel Dispatch and Method Thereof
Push for Sharing Instruction
Protocol for Transitioning in and Out of Zero-Power State
Low Overhead Soft Error Tolerant Flip Flop
Programmable Sample Clock for Empirical Setup Time Selection
Non-Destructive Sideband Reading of Processor State Information
Method and Apparatus for Data Decompression in the Presence of Memory Hierarchies
Hardware Based Multi-Dimensional Encryption
Hardware Monitoring and Decision Making for Transitioning in and Out of Low-Power State
Multiprocessor Communication Device and Methods Thereof
Method and Apparatus for Making a Processor Sideband Interface Adhere to Secure Mode Restrictions
Protocol for Power State Determination and Demotion
Work Balancing Scheduler for Processor Cores and Methods Thereof
Method and Apparatus for Regulating Power Consumption
Execute-Only Memory and Mechanism Enabling Execution from Execute-Only Memory for Minivisor
Minivisor Entry Point in Virtual Machine Monitor Address Space
Enhanced Control of Cpu Parking and Thread Rescheduling for Maximizing the Benefits of Low-Power State
Processor Power Management and Method
Processor Instructions for Improved Aes Encryption and Decryption
Error Detection Device and Methods Thereof
Processing of Streaming Data with a Keyed Delay
Frequency Locked Feedback Loop for Wireless Communications
Direct Memory Access (Dma) Address Translation in an Input/Output Memory Management Unit (Iommu)
Local Rollback for Fault-Tolerance in Parallel Computing Systems
Mechanism of Supporting Sub-Communicator Collectives with O(64) Counters as Opposed to One Counter for Each Sub-Communicator
Managing Concurrent Accesses to a Cache
Digital Phase Locked Loop System and Method
Cell Array and Density Features with Decoupling Capacitors
Low-Swing Signaling Scheme for Data Communication
Patent:
8,410,816 →
Application:
13/370,144 →
Identification of Localizable Function Calls
Sub-Circuit Models with Corner Instances for Vlsi Designs
Managing Concurrent Accesses to a Cache
High Throughput Decoding of Variable Length Data Symbols
Managing Concurrent Accesses to a Cache
High Throughput Decoding of Variable Length Data Symbols
Instruction Set Architecture with Extensible Register Addressing
Regular Expression Memory Region with Integrated Regular Expression Engine
Tracking Long Ghv in High Performance Out-of-Order Superscalar Processors
Increasing Efficiency of Data Payloads to Data Arrays Accessed Through Registers in a Distributed Virtual Bridge
Managing High-Coherence-Miss Cache Lines in Multi-Processor Computing Environments
Centralized Management of High-Contention Cache Lines in Multi-Processor Computing Environments
Cooperative Reduced Power Mode Suspension for High Input/Output ('I/O') Workloads
Managing Concurrent Accesses to a Cache
Increased Efficiency of Data Payloads to Data Arrays Accessed Through Registers in a Distributed Virtual Bridge
Parallel Data Processing
Methods, Apparatus and System for Tddb Testing
Multiple Core Processing with High Throughput Atomic Memory Operations
Creation and Management of Logical Volume Snapshots Under Hierarchical Storage System
Related Assignments
(6)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
Assignment of Assignor's Interest
Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
Security Agreement
Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
Assignment of Assignor's Interest
Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
Release of Security Interest
Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
Release of Security Interest
May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →