Granted Patent B1

US 7,055,006 · App. 10/426,755 · Granted May 30, 2006

Abstract

Claims (47)

1. A system, comprising:

at least one memory operable to store a first flag identifying whether a cache is disabled and a second flag identifying whether use of the cache is blocked; and

combinatorial logic operable to use the first and second flags to determine whether the cache is used during execution of at least one instruction by a processor, wherein the first flag identifies that the cache is enabled and the second flag identifies that the use of the cache is blocked when the processor is operating in a debugging mode.

2. The system of claim 1 , wherein:

the cache comprises a first cache;

the at least one memory is further operable to store a third flag identifying whether use of a second cache is blocked; and

the combinatorial logic is further operable to use the first and third flags to determine whether the second cache is used during the execution of the at least one instruction.

3. The system of claim 2 , wherein the combinatorial logic comprises:

an inverter operable to invert a value of the first flag;

a first AND gate operable to perform a logical AND operation involving the inverted value of the first flag and a value of the second flag to generate a first cache enable signal; and

a second AND gate operable to perform a logical AND operation involving the inverted value of the first flag and a value of the third flag to generate a second cache enable signal.

4. The system of claim 1 , wherein the at least one memory comprises a first register operable to store the first flag and a second register operable to store the second flag.

5. The system of claim 1 , wherein the cache comprises one of an instruction cache and a data cache.

6. The system of claim 1 , wherein the combinatorial logic is located in a core of the processor.

7. A processor, comprising:

an integer unit operable to execute integer instructions;

a floating point unit operable to execute floating point instructions;

a cache operable to store at least one of instructions to be executed and data used during execution of the instructions;

at least one memory operable to store a first flag identifying whether the cache is disabled and a second flag identifying whether use of the cache is blocked; and

combinatorial logic operable to use the first and second flags to determine whether the cache is used during execution of at least one of the instructions, wherein the first flag identifies that the cache is enabled and the second flag identifies that the use of the cache is blocked during execution of the at least one instruction in a debugging mode.

8. The processor of claim 7 , wherein:

the cache comprises a first cache;

the processor further comprises a second cache;

a third flag identifies whether use of the second cache is blocked; and

the combinatorial logic is further operable to use the first and third flags to determine whether the second cache is used during the execution of the at least one instruction.

9. The processor of claim 8 , wherein the combinatorial logic uses the first, second, and third flags to generate a first cache enable signal and a second cache enable signal, each cache enable signal identifying whether one of the caches can be used during the execution of the at least one instruction.

10. The processor of claim 9 , wherein the combinatorial logic comprises:

an inverter operable to invert a value of the first flag;

a first AND gate operable to perform a logical AND operation involving the inverted value of the first flag and a value of the second flag and to generate the first cache enable signal; and

a second AND gate operable to perform a logical AND operation involving the inverted value of the first flag and a value of the third flag and to generate the second cache enable signal.

11. The processor of claim 7 , wherein the at least one memory comprises a first register operable to store the first flag and a second register operable to store the second flag.

12. The processor of claim 7 , wherein the cache comprises one of an instruction cache and a data cache.

13. The processor of claim 7 , wherein the processor accesses an external memory when use of the cache is blocked.

14. The processor of claim 13 , wherein the external memory comprises a random access memory.

15. A method, comprising:

setting a first flag to enable a cache during execution of at least one instruction by a processor;

setting a second flag to block use of the cache during the execution of the at least one instruction;

determining whether access to the cache is blocked during the execution of the at least one instruction using the first and second flags; and

executing the at least one instruction in a debugging mode, wherein information is at least one of read from and written to an external memory instead of the cache.

16. The method of claim 15 , wherein determining whether access to the cache is blocked comprises:

inverting a value of the first flag; and

logically ANDing the inverted value of the first flag and a value of the second flag.

17. The method of claim 15 , wherein the cache comprises one of an instruction cache and a data cache.

18. The method of claim 15 , wherein the external memory comprises at least one of a random access memory and a hard drive.

19. The method of claim 15 , wherein setting the first and second flags comprises:

setting a cache disable bit in a first register; and

setting a cache blocking bit in a second register.

Assignments (8)