Cell array and density features with decoupling capacitors
View Patent ↗A method includes defining an array including a plurality of unit cells, receiving unit cell density parameters in a computing apparatus, and defining a plurality of sub-arrays of unit cells using the computing apparatus. The computing apparatus defines density features disposed between adjacent sub-arrays. The computing apparatus generates density feature density parameters based on the unit cell density parameters and at least one density limit.
1. A method, comprising:
defining an array including a plurality of unit cells;
receiving unit cell density parameters in a computing apparatus;
defining a plurality of sub-arrays of unit cells using the computing apparatus;
defining density features disposed between adjacent sub-arrays using the computing apparatus, wherein the computing apparatus generates density feature density parameters based on the unit cell density parameters and at least one density limit and wherein the computing apparatus defines shapes in the density features based on the density feature density parameters, wherein the shapes comprise decoupling capacitors; and
manufacturing an apparatus comprising the sub-arrays, the density features and the decoupling capacitors.
2. The method of claim 1 , wherein the computing apparatus solves an objective function for an area of the array subject to at least one constraint defined by the at least one density limit, the unit cell density parameters, and the density feature density parameter to generate the at least one density parameter of the density features.
3. The method of claim 2 , wherein the computing apparatus solves the objective function to determine a number of unit cells in each sub-array.
4. The method of claim 3 , wherein the unit cell density parameters include a unit cell width, the density feature density parameters include a density feature width, and the objective function defines the area of the array based on the density feature width, the unit cell width, and the number of unit cells in each sub-array.
5. The method of claim 4 , wherein the unit cell density parameters include a unit cell pattern density, the density feature density parameters include an density feature pattern density, and the at least one constraint compares the density limit to an array density defined by the density feature pattern density multiplied by the density feature width plus the unit cell pattern density multiplied by the unit cell width and the number of unit cells in each sub-array.
6. The method of claim 2 , wherein the at least one constraint comprises a first constraint based on a maximum density of the array and a second constraint based on a minimum density of the array.
7. The method of claim 2 , wherein the density feature density parameters comprise a density feature width and a density feature pattern density.
8. The method of claim 1 , wherein the computing apparatus is operable to repeat the defining of the plurality of sub-arrays and the defining of the density features for a plurality of array sizes and generate a look-up table including the density feature density parameters for each of the array sizes.
9. A semiconductor device, comprising:
an array of cells, wherein the array comprises:
a plurality of sub-arrays of the cells; and
density features disposed between adjacent sub-arrays, wherein the density features comprise decoupling capacitors.
10. A computer readable storage device encoded with data that, when implemented in a manufacturing facility, adapts the manufacturing facility to create an apparatus, comprising:
an array of cells, wherein the array comprises:
a plurality of sub-arrays of the cells; and
density features disposed between adjacent sub-arrays, wherein the density features comprise decoupling capacitors.