Granted Patent B1

US 7,130,951 · App. 10/419,091 · Granted Oct 31, 2006

Abstract

Claims (38)

1. A method of controlling a secure execution mode-capable processor, said method comprising:

operating in a non-secure execution mode;

entering a secure execution mode by initializing, from the non-secure execution mode, and executing a trusted secure operating system code segment that has been verified external to said secure execution mode-capable processor;

allowing a plurality of interrupts to interrupt said secure execution mode-capable processor when said secure execution mode-capable processor is operating in a non-secure execution mode; and

disabling said plurality of interrupts, including software interrupts, from interrupting said secure execution mode-capable processor and ensuring that said plurality of interrupts cannot be re-enabled, except by said trusted secure operating system code segment when said secure execution mode-capable processor is operating in said secure execution mode.

2. The method as recited in claim 1 , wherein disabling said plurality of interrupts includes holding said plurality of interrupts in a pending state until said plurality of interrupts is re-enabled.

3. The method as recited in claim 1 further comprising disabling said plurality of interrupts from interrupting said secure execution mode-capable processor in response to a system context switch upon entry into said trusted secure operating system code segment.

4. The method as recited in claim 1 further comprising disabling said plurality of interrupts by executing a clear global interrupt flag instruction.

5. The method as recited in claim 4 further comprising disabling debug traps in response to execution of said clear global interrupt flag instruction.

6. The method as recited in claim 4 further comprising enabling said plurality of interrupts in response to executing a set global interrupt flag instruction.

7. The method as recited in claim 6 further comprising executing said set global interrupt flag instruction and said clear global flag instruction during execution of said trusted secure operating system code segment.

8. The method as recited in claim 6 further comprising executing said clear global flag instruction in response to execution of a security initialization instruction.

9. The method as recited in claim 6 further comprising generating an invalid opcode fault in response to executing said set global interrupt flag instruction when said secure execution mode-capable processor is operating in said non-secure execution mode.

10. The method as recited in claim 6 further comprising generating an invalid opcode fault in response to executing said clear global interrupt flag instruction when said secure execution mode-capable processor is operating in said non-secure execution mode.

11. A secure execution mode-capable processor comprising:

execution logic configured to execute program instructions in a non-secure execution mode;

wherein the execution logic is further configured to execute program instructions in a secure execution mode in response to a secure execution mode initialization sequence initiated from the non-secure execution mode, wherein said program instructions include a trusted secure operating system code segment that has been verified external to said secure execution mode-capable processor; and

interrupt control logic coupled to said execution logic and configured to allow a plurality of interrupts to interrupt said execution logic during operation in a non-secure execution mode;

wherein said interrupt control logic is further configured to disable said plurality of interrupts, including software interrupts, from interrupting said execution logic and to ensure that said plurality of interrupts cannot be re-enabled, except by said trusted secure operating system code segment, during operation in said secure execution mode.

12. The secure execution mode-capable processor as recited in claim 11 , wherein said interrupt control logic is further configured to hold said plurality of interrupts in a pending state until said plurality of interrupts is re-enabled.

13. The secure execution mode-capable processor as recited in claim 11 , wherein said interrupt control logic is further configured to disable said plurality of interrupts from interrupting said execution logic in response to a system context switch upon entry into said trusted secure operating system code segment.

14. The secure execution mode-capable processor as recited in claim 11 further comprising a global interrupt disable storage configured to disable said plurality of interrupts from interrupting said execution logic during operation in said secure execution mode.

15. The secure execution mode-capable processor as recited in claim 14 , wherein said global interrupt disable storage is a global interrupt flag.

16. The secure execution mode-capable processor as recited in claim 14 , wherein said plurality of interrupts includes non-maskable interrupts.

17. The secure execution mode-capable processor as recited in claim 11 further comprising an interrupt disable storage configured to disable a portion of said plurality of interrupts from interrupting said execution logic during operation in said non-secure execution mode.

18. The secure execution mode-capable processor as recited in claim 17 , wherein said portion of said plurality of interrupts includes maskable interrupts.

19. The secure execution mode-capable processor as recited in claim 11 , wherein said interrupt control logic is further configured to disable said plurality of interrupts in response to said execution logic executing a clear global interrupt flag instruction.

20. The secure execution mode-capable processor as recited in claim 19 , wherein said interrupt control logic is further configured disable debug traps in response to execution of said clear global interrupt flag instruction.

21. The secure execution mode-capable processor as recited in claim 19 , wherein said interrupt control logic is further configured re-enable said plurality of interrupts in response to said execution logic executing a set global interrupt flag instruction during operation in said secure execution mode.

22. The secure execution mode-capable processor as recited in claim 21 , wherein said execution logic is further configured to execute said set global interrupt flag instruction and said clear global flag instruction during execution of said trusted secure operating system code segment.

23. The secure execution mode-capable processor as recited in claim 21 , wherein said execution logic is further configured to execute said clear global flag instruction in response to executing a security initialization instruction.

24. The secure execution mode-capable processor as recited in claim 21 , wherein said execution logic is further configured to generate a fault in response to executing said clear global interrupt flag instruction during operation in said non-secure execution mode.

25. The secure execution mode-capable processor as recited in claim 21 , wherein said execution logic is further configured to generate a fault in response to executing said set global interrupt flag instruction during operation in said non-secure execution mode.

26. A secure execution mode-capable processor comprising:

execution logic configured to execute program instructions in a non-secure execution mode;

wherein the execution logic is further configured to execute program instructions in a secure execution mode in response to a secure execution mode initialization sequence initiated from the non-secure execution mode, wherein said program instructions include a trusted secure operating system code segment that has been verified external to said secure execution mode-capable processor;

means for allowing a plurality of interrupts to interrupt said secure execution mode-capable processor when said secure execution mode-capable processor is operating in a non-secure execution mode; and

means for disabling said plurality of interrupts, including software interrupts, from interrupting said secure execution mode-capable processor and to ensure that said plurality of interrupts cannot be re-enabled, except by said trusted secure operating system code segment, when said secure execution mode-capable processor is operating in said secure execution mode.

Assignments (8)