IP Library Granted Patent US 8,060,882
Granted Patent B2
US 8,060,882 · App. 11/924,146 · Granted Nov 15, 2011

Processing tasks with failure recovery

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Quick Facts
Patent No.
US 8,060,882
App. No.
11/924,146
Granted
Nov 15, 2011
Kind
B2
Abstract

A method and apparatus is provided for processing tasks with failure recovery. The method includes storing one or more tasks in a queue, wherein each task has an associated exit routine, and determining at least one task to process based on a priority scheme. The method further includes processing the at least one task, and calling the exit routine based on determining that the task has not completed processing within a preselected period of time.

Claims (32)

1. A computer-implemented method, comprising:

storing one or more tasks in a queue, wherein each task has an associated exit routine;

determining at least one task to process based on a priority scheme;

processing the at least one task; and

calling the exit routine based on determining that the task has not completed processing within a preselected execution period.

2. The computer-implemented method of claim 1 , wherein storing the one or more tasks in the queue comprises generating an interrupt and storing the one or more tasks in the queue in response to detecting the interrupt.

3. The computer-implemented method of claim 1 , wherein determining at least one task to process based on the priority scheme comprises determining the at least one task based on a first-in, first-out priority scheme.

4. The computer-implemented method of claim 1 , wherein calling the exit routine comprises terminating the task currently processing and returning control to a task picker in the queue.

5. The computer-implemented method of claim 1 , wherein processing the at least one task comprises:

executing the task; and

programming a timer to generate an interrupt after a preselected time corresponding to the amount of time required for the task to complete executing.

6. A computing apparatus, comprising:

a queue having a task picker stored therein, the task picker being configured to:

determine if at least one task other than the task picker is stored in the queue;

execute the stored task upon determining that the stored task is stored in the queue; and

execute the task picker upon completing execution of the stored task and continue executing the task picker until a preselected event occurs.

7. The computing apparatus of claim 6 , wherein the preselected event comprises detection of an interrupt.

8. The computing apparatus of claim 6 , wherein the preselected event comprises detection of another task being present in the queue.

9. The computing apparatus of claim 6 , wherein each task stored in the queue comprises an exit routine to terminate that task.

10. The computing apparatus of claim 6 , wherein the task picker is configured to:

determine that more than one task is stored in the queue; and

select a task to execute from the one or more tasks based on a priority scheme.

11. The computing apparatus of claim 10 , wherein the priority scheme is a first-in, first-out scheme.

12. An article comprising one or more machine-readable storage media containing instructions that when executed enable a processor to:

store one or more tasks in a storage space, wherein each task has an associated exit routine;

determine at least one task to process based on a priority scheme;

process the at least one task; and

call the exit routine based on determining that the task cannot be processed to completion.

13. The article of claim 12 , wherein the instructions when executed enable the processor to generate an interrupt and store the one or more tasks in the storage space in response to detecting the interrupt.

14. The article of claim 12 , wherein the instructions when executed enable the processor to determine the at least one task based on a first-in, first-out priority scheme.

15. The article of claim 12 , wherein the instructions when executed enable the processor to terminate the task currently processing and return control to a task picker in the storage space.

16. The article of claim 12 , wherein the instructions when executed enable the processor to execute the task and to program a time to generate an interrupt at a preselected time, wherein the preselected time is greater than the time required for the task to complete executing.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2021
From: GLOBALFOUNDRIES US INC.
To: MEDIATEK INC.
Reel/Frame 055173/0781 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
AFFIRMATION OF PATENT ASSIGNMENT Recorded Aug 18, 2009
From: ADVANCED MICRO DEVICES, INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 023120/0426 →