Granted Patent B2

US 9,384,064 · App. 14/475,776 · Granted Jul 5, 2016

Abstract

Claims (25)

1. A processor comprising multiple processor cores and a bus configured to exchange data between the multiple processor cores, wherein each of the multiple processor cores comprises:

at least one processor register;

a cache configured to store at least one cache line of memory;

a load store unit configured to execute a memory command to exchange data between the cache and the at least one processor register;

an atomic memory operation unit configured to execute an atomic memory operation on the at least one cache line of memory; and

a high throughput register configured to store a status that indicates a high throughput status or a normal status, wherein the high throughput register affects the speed of the multiple processor cores;

wherein the load store unit is further operable to transfer the atomic memory operation to the atomic memory operation unit of a designated processor core selected from the multiple processor cores in the event the atomic memory operation status is the high throughput status, wherein the load store unit is further operable to transfer the atomic memory operation to the designated atomic memory operation unit using the bus.

2. The processor of claim 1 , wherein the load store unit is further operable to check if the memory command is an atomic memory operation and wherein the load store unit is further operable to detect the status.

3. The processor of claim 2 , and wherein the load store unit is further operable to detect the status if the memory command is an atomic memory operation, wherein the load store unit is further operable to set the high throughput register to the normal status after detecting the status.

4. The processor of claim 1 , wherein the atomic memory operation unit is further operable to execute the memory command if the status is the normal status and the memory command is an atomic memory operation.

5. The processor of claim 1 , wherein the load store unit is operable to retrieve the at least one cache line of memory via the bus from a memory address specified in the memory command, wherein the load store unit is further operable to determine the designated processor core by applying a function to the memory address.

6. The processor of any one of claim 1 , wherein the high throughput register is operable to store an atomic memory operation unit identifier for specifying the designated atomic memory operation unit, and wherein the load store unit is further operable to select the designated atomic memory operation unit using the atomic memory operation unit identifier.

7. The processor of claim 6 , wherein the load store unit is further operable to receive an identifier setting command, wherein execution of the identifier setting memory causes the load store unit to store the atomic memory operation unit identifier in the high throughput register.

8. The processor of claim 1 , wherein the bus is operable to transfer multiple memory commands to the other atomic memory operation unit in parallel.

9. The processor of claim 1 , wherein each of the multiple processor cores has multiple hardware threads, wherein each of the multiple processor cores is operable to implement simultaneous multithreading with the multiple hardware threads, wherein each of the multiple processor cores has a high throughput register dedicated to each of the multiple hardware threads.

10. The processor of claim 1 , wherein the load store unit is further operable to receive a status setting memory command, wherein execution of the status setting memory command causes the load store unit to set the status to the high throughput status.

11. The processor of claim 10 , wherein the status setting memory command is a no-operation command on an alternative implementation of the processor.

12. A method of operating a processor comprising multiple processor cores, wherein the processor comprises a bus for exchanging data between the multiple processor cores, wherein each of the multiple processor cores comprises at least one processor register, each of the multiple processor cores further comprises a cache for storing at least one cache line of memory, each of the multiple processor cores further comprises a load store unit for executing a memory command to exchange data between the cache and the at least one processor register, each of the multiple processor cores further comprises an atomic memory operation unit for executing an atomic memory operation on the at least one cache line of memory, each of the multiple processor cores further comprises a high throughput register for storing a status that indicates a high throughput status or a normal status, wherein the high throughput status affects the speed of the multiple processor cores, and the load store unit is further operable to transfer the atomic memory operation to the atomic memory operation unit of a designated processor core selected from the multiple processor cores in the event the atomic memory operation status is the high throughput status, the load store unit is further operable to transfer the atomic memory operation to the designated atomic memory operation unit using the bus, wherein the method comprises:

setting the status to the high throughput status on one or more of the multiple processor cores;

issuing one or more atomic memory operations that operates on a memory address on the one or more of the multiple processor cores; and

executing the one or more atomic memory operations using each of the one or more of the multiple processor cores.

13. A non-transitory computer readable storage medium comprising compiler instructions executable by a processor to perform a method of operating multiple core processors, the method comprising:

storing, via a high throughput register, a status that indicates a high throughput status or a normal status, wherein the high throughput register affects the speed of the multiple processor cores;

transferring an atomic memory, via a load store unit, to an atomic memory operation unit of a designated processor core selected from the multiple core processors in the event the atomic memory operation status is the high throughput status, wherein the high throughput status affects the speed of the multiple processor cores; and

transferring an atomic memory operation, via the load store unit, to the designated atomic memory operation unit using a bus.

Assignments (8)