Parallel instruction processing and operand integrity verification

1. A method comprising:

storing a first data to a first portion of a storage location of a storage component of a processing device in association with a first store operation, the storage location comprising the first portion and a second portion different than the first portion, the first portion and the second portion to store non-error correcting code data;

obtaining a second data from the storage location and obtaining first error-correcting code (ECC) data associated with the second data, the second data being stored at the storage location prior to the first data;

determining whether the storage location has a bit error at the second portion of the storage location based on the second data obtained from the storage location and based on the first ECC data; and

storing a third data to the second portion of the storage location in response to determining the storage location has a bit error at the second portion, wherein the third data is to correct the bit error.

2. The method of claim 1 , wherein obtaining the second data from the storage location comprises obtaining the second data in response to storing the first data.

3. The method of claim 1 , further comprising:

determining a second ECC data based on the third data in response to determining the storage location has a bit error at the second portion; and

overwriting the first ECC data of the storage component with the second ECC data.

4. The method of claim 1 , further comprising:

determining the third data based on the first data.

5. A method comprising:

performing a first store operation to a first storage location of a storage component;

performing a second store operation to a second storage location of the storage component subsequent to performing the first store operation;

determining the first storage location comprises a bit error not overwritten by the first store operation;

providing a first entry of an error handling table for the first store operation in response to determining that the first storage location comprises the bit error;

providing a second entry of the error handling table for the second store operation in response to determining that the first storage location comprises the bit error; and

correcting the bit error at the first storage location based on the first entry of the error handling table.

6. The method of claim 5 , wherein:

performing the first store operation comprises storing a first data to a first portion of the first storage location; and

determining the first storage location comprises the bit error comprises:

obtaining a second data stored at the first storage location prior to storing the first data;

determining the bit error at the first storage location based on the second data; and

determining the bit error occurs at a second portion of the first storage location separate from the first portion of the first storage location.

7. The method of claim 5 , wherein providing the first entry of the error handling table comprises:

determining a corrected data based on the bit error; and

providing the first entry having the corrected data and an indicator of a corresponding portion of the first storage location to be corrected using the corrected data.

8. The method of claim 7 , wherein correcting the bit error at the first storage location comprises:

accessing the corrected data from the first entry of the error handling table; and

overwriting a portion of the first storage location identified by the indicator with the corrected data.

9. The method of claim 8 , further comprising:

determining a first error correcting code (ECC) data based on the corrected data; and

overwriting a second ECC data of the storage component associated with the first storage location with the first ECC data.

10. The method of claim 5 , further comprising:

determining the second storage location comprises a bit error not overwritten by the second store operation; and

correcting the bit error at the second storage location based on the second entry of the error handling table.

11. The method of claim 10 , wherein:

providing the first entry of the error handling table comprises:

determining a first corrected data based on the bit error of the first storage location; and

providing the first entry having the first corrected data and a first indicator of a corresponding portion of the first storage location to be corrected using the first corrected data; and

providing the second entry of the error handling table comprises:

determining a second corrected data based on the bit error of the second storage location; and

providing the second entry having the second corrected data and a second indicator of a corresponding portion of the second storage location to be corrected using the second corrected data.

12. The method of claim 11 , wherein:

correcting the bit error at the first storage location comprises:

accessing the first corrected data from the first entry of the error handling table; and

overwriting a portion of the first storage location identified by the first indicator with the first corrected data; and

correcting the bit error at the second storage location comprises:

accessing the second corrected data from the second entry of the error handling table; and

overwriting a portion of the second storage location identified by the second indicator with the second corrected data.

13. A processing device comprising:

a store pipeline buffer to buffer a sequence of store operations;

a storage component to access a first store operation from the store pipeline buffer and to perform the first store operation to a storage location of the storage component;

an error detection unit to determine whether the storage location comprises a bit error not overwritten by the first store operation; and

an error correction unit to correct the bit error in the storage location in response to the first storage location comprising the bit error.

14. The processing device of claim 13 , further comprising:

a load/store unit (LSU) to buffer the sequence of store operations in the store pipeline buffer, the LSU being configured to stall processing of additional store operations in response to the storage location comprising the bit error.

15. The processing device of claim 13 , further comprising:

an error handling table comprising a plurality of entries; and

a store correction control unit configured to provide an entry of the error handling table for each of the sequence of store operations in response to the first storage location comprising the bit error.

16. The processing device of claim 15 , wherein:

the error detection unit is to provide a corrected data based on the bit error for storage at a first entry of the error handling table associated with the first store operation; and

the error correction unit is to access the first entry to obtain the corrected data and to overwrite a corresponding portion of the storage location in response to the storage location comprising the bit error.

17. The processing device of claim 15 , wherein:

the error correction unit is to:

access the first entry to obtain the corrected data in response to receiving a load operation associated with the storage location; and

provide data in response to the load operation based on the corrected data.

18. The processing device of claim 13 , wherein:

the error correction unit is to abstain from correcting the bit error based on the first entry in response to determining that the second store operation results in the bit error being overwritten.