Asymmetric control of high-speed bidirectional signaling

1. A system comprising:

a slave device; and

a master device coupled to the slave device and configured to control data transfer between the master device and the slave device;

wherein the master device is configured to adaptively modify transmit characteristics based upon information received from the slave device, subsequent to adaptively modifying a phase alignment of a receiver sample clock of the master device based upon cyclic redundancy code (CRC) information received from the slave device via one or more unidirectional CRC data paths, wherein the CRC information corresponds to data transmitted between the master device and the slave device via a plurality of bidirectional data paths;

wherein the CRC information received from the slave device includes data eye information sent via the one or more unidirectional CRC data paths, wherein the data eye information corresponds to an edge position of data signal transitions received by the slave device on the plurality of bidirectional data paths; and

wherein the CRC information and the data eye information are multiplexed on the one or more unidirectional CRC data paths, and wherein the CRC information sent from the slave device during different bit times dependent upon whether the master device is writing or reading the data transmitted between the master device and the slave device via a plurality of bidirectional data paths.

2. The system as recited in claim 1 , wherein the master device is configured to adaptively modify a phase alignment of the data transmitted by the master device via the plurality of bidirectional data paths depending upon the CRC information and the data eye information.

3. The system as recited in claim 2 , wherein the master device is configured to transmit a predetermined pattern to the slave device and to adaptively modify data path equalization coefficients within the master device for each path of the plurality of bidirectional data paths based upon the corresponding CRC information and the data eye information.

4. The system as recited in claim 1 , wherein the master device is configured to store a predetermined data pattern within the slave device via a plurality of bidirectional data paths, wherein the information received from the slave device includes the predetermined pattern.

5. The system as recited in claim 4 , wherein the master device is configured to adaptively modify a phase alignment of a receiver sample clock of the master device dependent upon the predetermined data pattern.

6. The system as recited in claim 4 , wherein the master device is configured to adaptively modify data path equalization coefficients within the master device for each path of the plurality of bidirectional data paths based upon the predetermined data pattern.

7. The system as recited in claim 1 , wherein the slave device sends data corresponding to a same critical word during a first bit time and a second bit time of a fixed number of bit times in response to the master device requesting data during a read operation.

8. The system as recited in claim 7 , wherein the slave device sends data corresponding to a third data byte of a data block having 16 data bytes via the one or more unidirectional CRC data paths during the first four bit times of a read operation.

9. The system as recited in claim 8 , wherein the slave device sends the CRC information via the one or more unidirectional CRC data paths during a next successive bit time after the bit time used to send the third data byte during a read operation.

10. The system as recited in claim 1 , wherein master device is configured to write the data transmitted by the master device via the plurality of bidirectional data paths to the slave device using a byte write operation, during which the master device writes a byte mask during the first four bit times of the byte write operation.

11. The system as recited in claim 10 , wherein the slave device samples the byte mask during the third bit time of the first four bit times.

12. A method comprising:

a master device controlling data transfer between the master device and a slave device; and

the master device adaptively modifying transmit characteristics based upon information received from the slave device, subsequent to adaptively modifying a phase alignment of a receiver sample clock of the master device based upon cyclic redundancy code (CRC) information received from the slave device via one or more unidirectional CRC data paths, wherein the CRC information corresponds to data transmitted between the master device and the slave device via a plurality of bidirectional data paths;

wherein the CRC information received from the slave device includes data eye information sent via the one or more unidirectional CRC data paths, wherein the data eye information corresponds to an edge position of data signal transitions received by the slave device on the plurality of bidirectional data paths; and

wherein the CRC information and the data eye information are multiplexed on the one or more unidirectional CRC data paths, and wherein the CRC information is sent from the slave device during different bit times dependent upon whether the master device is writing or reading the data transmitted between the master device and the slave device via a plurality of bidirectional data paths.

13. The method as recited claim 12 , wherein the master device is configured to adaptively modify a phase alignment of the data transmitted by the master device via the plurality of bidirectional data paths depending upon the CRC information and the data eye information.

14. The method as recited in claim 13 , further comprising the master device transmitting a predetermined pattern to the slave device and adaptively modifying data path equalization coefficients within the master device for each path of the plurality of bidirectional data paths based upon the corresponding CRC information and the data eye information.

15. The method as recited in claim 12 , further comprising the master device storing a predetermined data pattern within the slave device via a plurality of bidirectional data paths, wherein the information received from the slave device includes the predetermined pattern.

16. The method as recited in claim 15 , further comprising the master device adaptively modifying a phase alignment of a receiver sample clock of the master device dependent upon the predetermined data pattern.

17. The method as recited in claim 15 , further comprising the master device adaptively modifying data path equalization coefficients within the master device for each path of the plurality of bidirectional data paths based upon the predetermined data pattern.

18. A memory subsystem comprising:

a memory device; and

a memory controller coupled to the memory device and configured to control data transfer between the memory controller and the memory device; and

wherein the memory controller is configured to adaptively modify transmit characteristics based upon information received from the memory device, subsequent to adaptively modifying a phase alignment of a receiver sample clock of the memory controller based upon cyclic redundancy code (CRC) information received from the memory device via one or more unidirectional CRC data paths, wherein the CRC information corresponds to data transmitted between the memory controller and the memory device via a plurality of bidirectional data paths;

wherein the CRC information received from the memory device includes data eye information sent via the one or more unidirectional CRC data paths, wherein the data eye information corresponds to an edge position of data signal transitions received by the memory device on the plurality of bidirectional data paths; and

wherein the CRC information and the data eye information are multiplexed on the one or more unidirectional CRC data paths, and wherein the CRC information is sent from the memory device during different bit times dependent upon whether the memory controller is writing or reading the data transmitted between the memory controller and the memory device via a plurality of bidirectional data paths.