Error detection device and methods thereof
View Patent ↗A first error detection for a first data word is performed using a first error correction code associated with the first data word. In response to the first error detection indicating a first uncorrectable error at the first data word based upon the first error correction code, a second error detection for a plurality of data words including the first data word and a second data word is performed using a second error correction code based upon the first and second data words.
1. A method, comprising:
performing a first error detection for a first data word using a first error correction code (ECC) based upon the first data word; and
in response to the first error detection indicating an error at the first data word that is uncorrectable based upon the first ECC, performing a second error detection for a plurality of data words including the first data word and a second data word, using a second ECC based upon the first and second data words, wherein the first error detection is based upon a first algorithm, the second error detection is based upon a second algorithm, and wherein error detection based upon the first algorithm is performed on data words accessed from a first cache and from a second cache, and error detection based upon the second algorithm is performed on data words accessed from the first cache and not performed on data words accessed from the second cache.
2. The method of claim 1 , wherein the first ECC, the second ECC and the plurality of data words are received from the first cache.
3. The method of claim 1 further comprising:
in response to the first error detection indicating an error at the first data word that is correctable based upon the first ECC, correcting the correctable error at the first data word to generate a corrected first data word; and
storing the corrected first data word and the first ECC to the second cache.
4. The method of claim 1 , further comprising:
in response to the first error detection indicating an error at the first data word that is correctable based upon the first ECC, correcting the correctable error at the first data word to generate a corrected first data word; and
storing the corrected first data word and not the second ECC to the second cache.
5. The method of claim 1 , wherein the second ECC includes a greater number of data bits and can correct a greater number of bit errors than the first ECC.
6. The method of claim 1 , further comprising:
performing a third error detection for the second data word using a third ECC; and in response to the third error detection indicating an error at the second data word that is uncorrectable based upon the third ECC, performing the second error detection for the plurality of data words including the first data word and the second data word, using the second ECC.
7. The method of claim 6 , wherein the first data word and the second data word are associated with a common burst access at the first cache.
8. The method of claim 1 , wherein performing first error detection comprises performing first error detection in response to receiving the first data word and the first ECC from the first cache, and further comprising:
correcting a correctable error at the at the first data word in response to detecting a correctable error; and
storing the corrected first data word at the second cache.
9. The method of claim 8 , wherein storing the corrected data comprises storing the corrected data at the second cache with the first ECC.
10. The method of claim 1 , wherein the first error detection is part of an error detection/correction algorithm that deterministically detects two or fewer bit errors and corrects a single-bit error based upon the first ECC, and the second error detection is part of an error detection/correction algorithm that deterministically detects three or fewer bit errors and corrects two or fewer bit error based upon the ECC.
11. The method of claim 1 , wherein correcting the correctable error at the first data word further comprises providing the corrected first data word to a central processing unit.
12. A method, comprising:
receiving a plurality of data words including a first data word and a second data word;
determining a first ECC based on the first data word and not on the second data word;
determining a second ECC based on the second data word and not on the first data word;
determining a third ECC based on the plurality of data words; and
storing the first data word, the second data word, the first ECC, the second ECC, and the third ECC to a memory, wherein storing comprises:
storing the first ECC and the first data word wherein the first data word and the first ECC are retrieved from Memory based on a first memory access;
storing a first portion of the third ECC and the first data word wherein the first portion and the first data word are retrieved from memory based on the first memory access;
storing the second ECC and the second data word wherein the second data word and the second ECC are retrieved from memory based on a second memory access; and
storing a second portion of the third ECC and the second data word wherein the second portion and the second data word are retrieved from memory based on the second memory access.
13. The method of claim 12 , further comprising:
performing a first error detection for the first data word using the first ECC; and
in response to the first error detection indicating a first uncorrected error, performing a second error detection for the first data word and the second data word using the third ECC.
14. The method of claim 12 , further comprising:
performing a third error detection for the second data word using the second ECC; and
in response to the third error detection indicating a first uncorrectable error, performing a second error detection for the first data word and the second data word using the third ECC.
15. A device, comprising:
a first memory configured to store:
a first data word;
a first ECC configured to detect and correct an error with the first data word, the first ECC based only upon the first data word; and
a second ECC based upon a plurality of data words including the first data word and a second data word;
a first ECC module coupled to the first memory, the first ECC module configured to:
perform a first error detection for the first data word using the first ECC; and
a second ECC module coupled to the first memory, the second ECC module configured to:
perform a second error detection for the plurality of data words using the second ECC in response to the first error detection indicating a first uncorrected error, wherein the first error detection is based upon a first algorithm, the second error detection is based upon a second algorithm, and wherein error detection based upon the first algorithm is performed on data words accessed from the first memory and from a second memory, and error detection based upon the second algorithm is performed on data words accessed from the first memory and not performed on data words accessed from the second memory.
16. The device of claim 15 , wherein:
the first memory is configured to store:
a second data word; and
a third ECC based only upon the second data word; and
the first ECC module is configured to:
perform a third error detection for the second data word using the third ECC; and
in response to the third error detection indicating a second error, performing a fourth error detection for the plurality of data words using the second ECC.
17. The device of claim 16 , wherein the first ECC module is configured to:
determine the first ECC based only on the first data word;
determine the third ECC based only on the second data word; and
wherein the second ECC module is configured to:
determine the second ECC based on the plurality of data words.
18. The device of claim 15 , wherein the second ECC module is configured to determine first corrected data in response to the second error detection and the second memory is configured to receive the first corrected data.
19. The device of claim 15 , wherein the first memory comprises a first cache associated with a data processing device and the second memory comprises a second cache associated with the data processing device.
20. The device of claim 15 , wherein the first data word and the second data word are associated with a common burst access at the first memory.