Non-destructive sideband reading of processor state information
View Patent ↗A processor receives a command via a sideband interface on the processor to read processor state information, e.g., CPUID information. The sideband interface provides the command information to a microcode engine in the processor that executes the command to retrieve the designated processor state information at an appropriate instruction boundary and retrieves the processor state information. That processor information is stored in local buffers in the sideband interface to avoid modifying processor state. After the microcode engine completes retrieval of the information and the sideband interface command is complete, execution returns to the normal flow in the processor. Thus, the processor state information may be obtained non-destructively during processor runtime.
1. A method comprising:
supplying a processor during runtime via a sideband interface on the processor with a command to read processor state information;
responsive to the command, the processor retrieving requested processor state information from storage elements in the processor; and
storing the requested processor state information in storage elements local to the sideband interface without affecting processor state.
2. The method as recited in claim 1 wherein the processor state information identifies at least one of processor features or capabilities.
3. The method as recited in claim 2 wherein the processor state information corresponds to information from a CPUID command.
4. The method as recited in claim 1 further comprising supplying the processor state information through the sideband interface to a device that sent the command.
5. The method as recited in claim 1 further comprising the processor responding to the command by executing microcode to obtain the processor state information.
6. The method as recited in claim 1 wherein the processor state information is obtained without modifying general purpose registers in the processor.
7. The method as recited in claim 1 , further comprising storing the processor state information in non-volatile storage elements in the processor.
8. The method as recited in claim 1 further comprising:
interrupting execution of processor instructions to retrieve the processor state information; and
returning to execution of processor instructions immediately upon completing the storing of the requested processor state information.
9. A processor comprising:
a sideband interface responsive to a command received on the sideband interface;
first storage locations local to the sideband interface and separate from processor general purpose registers;
second storage locations for storing processor state information; and
a microcode execution engine responsive to the sideband interface to retrieve processor state information and store the processor state information in the first storage locations without modifying one or more general purpose registers in the processor.
10. The processor as recited in claim 9 wherein the processor state information retrieved is processor identification information.
11. The processor as recited in claim 9 wherein the processor state information corresponds to information associated with a CPUID command.
12. The processor as recited in claim 9 further comprising non-volatile memory storing the processor state information.
13. The processor as recited in claim 9 further comprising volatile memory to store the processor state information.
14. A method comprising:
supplying a processor during runtime via a sideband interface on the processor with a command to read platform state information;
responsive to the command, the processor retrieving requested platform state information from storage elements in the platform; and
storing the requested platform state information in storage elements local to the sideband interface without affecting processor state.
15. The method as recited in claim 14 wherein the platform state information includes at least one of information external to the processor and information internal to the processor.
16. The method as recited in claim 14 wherein the platform state information includes information from system memory.
17. The method as recited in claim 14 wherein the platform state information includes information received over an input/output communications link coupled to the processor.
18. A processor comprising:
a sideband interface responsive to a command received on the sideband interface;
first storage locations local to the sideband interface and separate from processor general purpose registers; and
a microcode execution engine responsive to the sideband interface to retrieve platform state information and store the platform state information in the first storage locations without modifying one or more general purpose registers in the processor.
19. The processor as recited in claim 18 wherein the platform state information retrieved is from system memory.
20. The processor as recited in claim 18 wherein the platform state information includes information received over an input/output communications link coupled to the processor.