Digital phase locked loop system and method

1. A phase locked loop control system comprising:

a reference clock input for receiving a reference clock signal;

a digital controlled oscillator configured to output an adjustable clock signal;

a digital detector coupled between the reference clock input and an input of the controlled oscillator, the detector coupled to an output of the oscillator and configured for applying control signals to the oscillator for setting output operating signal frequency in accordance with detected frequency of the oscillator output clock signal; and

a counter coupled to the oscillator output; wherein:

the digital detector comprises a control signal generator configured to generate a plurality of binary control signals respectively output at a plurality of control signal generator output terminals, a comparator having a first comparator input coupled to the reference clock input, a second comparator input coupled to the counter, and a comparator output coupled to the control signal generator; and

the oscillator comprises a plurality of decoder logic cells having inputs respectively coupled to the control signal generator output terminals;

wherein the phase of the output signal is selectively adjusted by the digital detector control signals during each input clock cycle.

2. A phase locked loop control system as recited in claim 1 , wherein the control signal generator is responsive to the divided reference clock signal.

3. A phase locked loop control system comprising:

a reference clock input for receiving a reference clock signal;

a digital controlled oscillator configured to output an adjustable clock signal;

an input divider coupled to the reference clock input for dividing the reference clock signal to one of a plurality of preset dividing rates; and

an output divider coupled to the oscillator output for dividing the oscillator output signal to one of a plurality of preset dividing rates; and

a digital detector coupled between the reference clock input and an input of the controlled oscillator, the detector coupled to an output of the oscillator and configured for applying control signals to the oscillator for setting output operating signal frequency in accordance with detected frequency of the oscillator output clock signal;

wherein the phase of the output signal is selectively adjusted by the digital detector control signals during each input clock cycle;

the digital detector comprises a control signal generator configured to generate a plurality of binary control signals respectively output at a plurality of control signal generator output terminals; and

the oscillator comprises a plurality of decoder logic cells having inputs respectively coupled to the control signal generator output terminals;

and further comprising a counter coupled to the oscillator output;

wherein the digital detector comprises a comparator having a first comparator input coupled to the input divider, a second comparator input coupled to the counter, and a comparator output coupled to the control signal generator.

4. A phase locked loop control system as recited in claim 3 , wherein the input divider comprises a control input for selecting a dividing rate for the received reference clock signal and the output divider comprises a control input for selecting a dividing rate for the output signal.

5. A phase locked loop control system as recited in claim 3 , wherein the digital detector further comprises a shift generator having a first input coupled to the input divider and a second input coupled to the comparator and an output coupled to the oscillator.

6. A phase locked loop control system as recited in claim 5 , wherein the shift generator comprises a plurality of flip-flops connected in series, each flip-flop having an output coupled to a respective control input of the oscillator.

7. A phase locked loop control system comprising:

a reference clock input for receiving a reference clock signal;

a digital controlled oscillator configured to output an adjustable clock signal;

an input divider coupled to the reference clock input for dividing the reference clock signal to one of a plurality of preset dividing rates; and

an output divider coupled to the oscillator output for dividing the oscillator output signal to one of a plurality of preset dividing rates; and

a digital detector coupled between the reference clock input and an input of the controlled oscillator, the detector coupled to an output of the oscillator and configured for applying control signals to the oscillator for setting output operating signal frequency in accordance with detected frequency of the oscillator output clock signal;

wherein the phase of the output signal is selectively adjusted by the digital detector control signals during each input clock cycle;

the digital detector comprises a control signal generator configured to generate a plurality of binary control signals respectively output at a plurality of control signal generator output terminals; and

the oscillator comprises a plurality of decoder logic cells having inputs respectively coupled to the control signal generator output terminals;

and wherein the plurality of decoder logic cells comprises a first group of large delay cells and a second decoder group of small delay cells.

8. A phase locked loop control system as recited in claim 7 , wherein the DCO comprise NAND gates as its basic delay cell.

9. A phase locked loop control system as recited in claim 7 , wherein the oscillator further comprises a plurality of logic load elements having inputs respectively connected to output terminals of the control signal generator;

wherein the logic elements are coupled to the detector for receiving the control signals for adjusting the phase of the output signal.

10. A phase locked loop control system comprising:

a reference clock input for receiving a reference clock signal;

a digital controlled oscillator configured to output an adjustable clock signal;

an input divider coupled to the reference clock input for dividing the reference clock signal to one of a plurality of preset dividing rates; and

an output divider coupled to the oscillator output for dividing the oscillator output signal to one of a plurality of preset dividing rates; and

a digital detector coupled between the reference clock input and an input of the controlled oscillator, the detector coupled to an output of the oscillator and configured for applying control signals to the oscillator for setting output operating signal frequency in accordance with detected frequency of the oscillator output clock signal;

wherein the phase of the output signal is selectively adjusted by the digital detector control signals during each input clock cycle;

the digital detector comprises a control signal generator configured to generate a plurality of binary control signals respectively output at a plurality of control signal generator output terminals; and

the oscillator comprises a plurality of decoder logic cells having inputs respectively coupled to the control signal generator output terminals;

and wherein the wherein the digital detector further comprises an asynchronous cycle control generator having an input coupled to the oscillator output signal; and

wherein the control signal generator binary output control signals are fixed to capture the frequency of the reference clock signal and the asynchronous cycle control generator is responsive to the phase of the oscillator output signal relative to the divided reference signal.

11. A phase locked loop control system as recited in claim 10 , wherein the digital detector further comprises a lock detector responsive to the dividing rates of the input divider and output divider to generate a lock output signal.

12. A phase locked loop control system as recited in claim 11 , wherein the digital detector further comprises an unlock generator for outputting a reset signal in response to the lock output signal if a change in the dividing rates of either the input divider or output divider has been detected by the lock detector.