Patent Assignment
Reel/Frame 047660/0203
Security Agreement
Recorded: 2018-11-27
Pages: 44
Assignor
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Executed: 2018-11-27
Assignee
WILMINGTON TRUST, NATIONAL ASSOCIATION
1100 NORTH MARKET STREET, WILMINGTON, DELAWARE, 19801
Covered Properties
(607)
Non-Volatile Memory Manufacturing Method Using Sti Trench Implantation
Slot designs in wide metal lines
Method and Apparatus for Removing Radiation Side Lobes
Mask and Method to Pattern Chromeless Phase Lithography Contact Hole
Grain Boundary Blocking for Stress Migration and Electromigration Improvement in Cu Interconnects
Formation of Strained Si Channel and SI1-Xgex Source/Drain Structures Using Laser Annealing
Embedded Stressor Structure and Process
Selective Stress Relaxation of Contact Etch Stop Layer Through Layout Design
Integrated Circuit Isolation System
Method to Control Source/Drain Stressor Profiles for Stress Engineering
Integrated Circuit System Including Nitride Layer Technology
Integrated Circuit System with Contact Distribution Film
Semiconductor System Using Germanium Condensation
Integrated Circuit with Self-Aligned Line and Via
Semiconductor Local Interconnect and Contact
Integrated Circuit Having a Plurality of Mosfet Devices
Integrated Circuit System with Double Doped Drain Transistor
Capacitor Top Plate Over Source/Drain to Form a 1T Memory Device
Large Tuning Range Junction Varactor
Structure and Method to Form Source and Drain Regions Over Doped Depletion Regions
Transformer with Effective High Turn Ratio
Integrated Circuit Shield Structure
Integrated Circuit System with Clean Surfaces
Method for Fabricating Semiconductor Devices with Reduced Junction Diffusion
Method of Fabricating a Nitrogenated Silicon Oxide Layer and Mos Device Having Same
Poly Profile Engineering to Modulate Spacer Induced Stress for Device Enhancement
Critical Dimension for Trench and Vias
Wafer Handling System for a Loadlock
Statistical Optical Proximity Correction
Integrated Circuit and Method of Fabrication Thereof
Thin Film Etching Method and Semiconductor Device Fabrication Using Same
Process for Fabricating a Semiconductor Device Having Embedded Epitaxial Regions
Tunable High Quality Factor Inductor
Strain-Direct-On-Insulator (Sdoi) Substrate and Method of Forming
Methods and Apparatus for White Space Reduction in a Production Facility
Method for Fabricating Device Structures Having a Variation in Electrical Conductivity
Method for Fabricating a Semiconductor Device Having an Epitaxial Channel and Transistor Having Same
Integrated Circuit System Employing Resistance Altering Techniques
Polishing Method with Inert Gas Injection
Methods for Normalizing Strain in a Semiconductor Device
Planarized Passivation Layer for Semiconductor Devices
Integrated Circuit System Employing Sacrificial Spacers
Multi-Variable Regression for Metrology
Method for Performing a Shelf Lifetime Acceleration Test
Method for Reducing Silicide Defects in Integrated Circuits
Method of Forming a Nanostructure
Integrated Circuit System Employing Back End of Line via Techniques
Stress Liner for Stress Engineering
High Performance Ldmos Device Having Enhanced Dielectric Strain Layer
Diffusion Barrier and Method of Formation Thereof
System for Determining Potential Lot Consolidation During Manufacturing
Integrated Circuit System Employing Alternating Conductive Layers
Semiconductor Fabrication Process Including an Sige Rework Method
Polishing with Enhanced Uniformity
Reliable Interconnects
Interconnects with Improved Tddb
Method and Apparatus to Reduce Thermal Variations Within an Integrated Circuit Die Using Thermal Proximity Correction
Integrated Circuit System with Antenna
Method to Remove Spacer After Salicidation to Enhance Contact Etch Stop Liner Stress on Mos
Integrated Circuit Structure with Electrical Strap and Its Method of Forming
Optical Color Sensor System
Integrated Circuit System Employing an Elevated Drain
Method for Forming a Shallow Junction Region Using Defect Engineering and Laser Annealing
Tunable Spacers for Improved Gapfill
Method to Prevent Corrosion of Bond Pad Structure
Memory Cell Structure and Method for Fabrication Thereof
Fabricating Method for Crack Stop Structure Enhancement of Integrated Circuit Seal Ring
Method of Forming a High Voltage Device
Methods for Enhancing Photolithography Patterning
Laser Annealing
Reliable Memory Cell
Integrated Circuit System with a Floating Dielectric Region and Method of Manufacture Thereof
Integrated Circuit Packaging System and Method of Manufacture Thereof
Integrated Circuit Communication System with Differential Signal and Method of Manufacture Thereof
Patterning Nanocrystal Layers
Non-Volatile Memory Utilizing Impact Ionization and Tunnelling and Method of Manufacturing Thereof
Mask System Employing Substantially Circular Optical Proximity Correction Target and Method of Manufacture Thereof
Method of Manufacture an Integrated Circuit System with Through Silicon Via
Integrated Circuit System with Hierarchical Capacitor and Method of Manufacture Thereof
Integrated Circuit System with Sub-Geometry Removal and Method of Manufacture Thereof
Integrated Circuit System with High Voltage Transistor and Method of Manufacture Thereof
High Voltage Device
Semiconductor Intra-Field Dose Correction
Modulation of Stress in Stress Film Through Ion Implantation and Its Application in Stress Memorization Technique
Defect Monitoring in Semiconductor Device Fabrication
Integrated Circuit System with Sealring and Method of Manufacture Thereof
Asymmetrical Transistor Device and Method of Fabrication
Triggered Silicon Controlled Rectifier for Rf Esd Protection
Reliable Interconnect for Semiconductor Device
Double Anneal with Improved Reliability for Dual Contact Etch Stop Liner Scheme
Method of Fabricating a Silicon Tunneling Field Effect Transistor (Tfet) with High Drive Current
Integrated Circuit Packaging System with Core Region and Bond Pad and Method of Manufacture Thereof
Spacer-Less Low-K Dielectric Processes
Mos Varactors with Large Tuning Range
Defect Detection Recipe Definition
Test Chiplets for Devices
Control Gate
Methods for Reducing Loading Effects During Film Formation
Liquid Immersion Scanning Exposure System Using an Immersion Liquid Confined Within a Lens Hood
Memory Cell with Improved Retention
Hybrid Transistor
Method of Fabrication an Integrated Circuit
Mask and Method to Pattern Chromeless Phase Lithography Contact Hole
Angled-Wedge Chrome-Face Wall for Intensity Balance of Alternating Phase Shift Mask
Method for Fabricating Semiconductor Devices Using Stress Engineering
Selective Sti Stress Relaxation Through Ion Implantation
Integrated Circuit System Employing Low-K Dielectrics and Method of Manufacture Thereof
Novel Method to Tune Narrow Width Effect with Raised S/D Structure
Finfet with Novel Body Contact for Multiple Vt Applications
Novel Methods to Reduce Gate Contact Resistance for Ac Reff Reduction
Method for Reducing Silicide Defects in Integrated Circuits
Consistency Check in Device Design and Manufacturing
Method for Fabricating Nano Devices
Nested and Isolated Transistors with Reduced Impedance Difference
Strained Channel Transistor and Method of Fabrication Thereof
Strained Channel Transistor Structure and Method
Methods of Forming Cmos Transistors Using Tensile Stress Layers and Hydrogen Plasma Treatment
Reliable Interconnects
Eeprom Cell
Dielectric Stack
Eeprom Cell
Self-Aligned Body Fully Isolated Device
Ldmos Using a Combination of Enhanced Dielectric Stress Layer and Dummy Gates
Method and System for Introducing Physical Damage into an Integrated Circuit Device for Verifying Testing Program and Its Results
Integrated Circuit System with Bandgap Material and Method of Manufacture Thereof
High-K Metal Gate Device
Semiconductor Structure Including High Voltage Device
Finfet
Finfet with Stressors
Modifying Growth Rate of a Device Layer
Method to Reduce Depth Delta Between Dense and Wide Features in Dual Damascene Structures
Integrated Circuit System with Ultra-Low K Dielectric and Method of Manufacture Thereof
Reliable Interconnect Integration Scheme
P-Channel Flash with Enhanced Band-to-Band Tunneling Hot Electron Injection
Self-Aligned Contact for Replacement Metal Gate and Silicide Last Processes
Channel Surface Technique for Fabrication of Finfet Devices
Ldmos with Improved Breakdown Voltage
Ldmos with Two Gate Stacks Having Different Work Functions for Improved Breakdown Voltage
Package Interconnects
Arc Residue-Free Etching
Hybrid TSV and Method for Forming the Same
Scheme for Planarizing Through-Silicon Vias
Integrated Transformer
Structures and Methods of Improving Reliability of Non-Volatile Memory Devices
Nano-Electro-Mechanical System (Nems) Structures with Actuatable Semiconductor Fin on Bulk Substrates
High-K Metal Gate Device
Method and Apparatus for Creating and Managing Waiver Descriptions for Design Verification
Method for Forming Fully Relaxed Silicon Germanium on Silicon
Integrated Circuit System with Through Silicon via and Method of Manufacture Thereof
Digital Phase Locked Loop System and Method
Ip Protection
Package Interconnects
Planarized Passivation Layer for Semiconductor Devices
Poly Profile Engineering to Modulate Spacer Induced Stress for Device Enhancement
Memory Cell with Decoupled Channels
Split-Gate Flash Memory Exhibiting Reduced Interference
Method for Fabricating a Semiconductor Device Having an Epitaxial Channel and Transistor Having Same
Method and Apparatus for Preemptive Design Verification via Partial Pattern Matching
Method and Device for a Split-Gate Flash Memory with an Extended Word Gate Below a Channel Region
Double Gated Flash Memory
Method to Control Source/Drain Stressor Profiles for Stress Engineering
Semiconductor Device Including an N-Well Structure
Methodology for Performing Post Layer Generation Check
Damascene Process for Aligning and Bonding Through-Silicon-via Based 3D Integrated Circuit Stacks
Integrated Circuit System with Hierarchical Capacitor and Method of Manufacture Thereof
Trench Transistor
Integrated Circuit and Method of Fabrication Thereof
Reliable Contacts
Method and Apparatus for Pattern Adjusted Timing via Pattern Matching
Integration of Envm, Rmg, and Hkmg Modules
High Voltage Device
Method for Fabricating Semiconductor Devices with Reduced Junction Diffusion
Interconnects with Improved Tddb
TSV Backside Processing Using Copper Damascene Interconnect Technology
Method for Forming an Air Gap Around a Through-Silicon Via
Methods of Protecting Elevated Polysilicon Structures During Etching Processes
High Performance Ldmos Device Having Enhanced Dielectric Strain Layer
Step-Like Spacer Profile
Efficient Transfer of Materials in Manufacturing
High Voltage Device
Low Ohmic Contacts
Spacer Profile Engineering Using Films with Continuously Increased Etch Rate from Inner to Outer Surface
Charging Controlled Rram Device, and Methods of Making Same
Crack-Arresting Structure for Through-Silicon Vias
Asymmetrical Transistor Device and Method of Fabrication
Methods for Pfet Fabrication Using Apm Solutions
Latch Up Detection
Esd Protection Without Latch-Up
Compact Rram Device and Methods of Making Same
Esd-Robust I/O Driver Circuits
Cross-Domain Esd Protection Scheme
Three Dimensional Rram Device, and Methods of Making Same
Back-Side Mom/Mim Devices
Power Clamp for High Voltage Integrated Circuits
Driver-Based Distributed Multi-Path Esd Scheme
Rram Device with an Embedded Selector Structure and Methods of Making Same
Esd Protection Device with a Tunable Holding Voltage for a High Voltage Programming Pad
Integrated Circuit System with Through Silicon via and Method of Manufacture Thereof
Method and Apparatus for Esd Circuits
Gate Dielectric Protection
Esd Protection for High Voltage Applications
Late in-Situ Doped Sige Junctions for Pmos Devices on 28 Nm Low Power/High Performance Technologies Using a Silicon Oxide Encapsulation, Early Halo and Extension Implantations
Middle in-Situ Doped Sige Junctions for Pmos Devices on 28 Nm Low Power/High Performance Technologies Using a Silicon Oxide Encapsulation, Early Halo and Extension Implantations
Esd Protection Device for Circuits with Multiple Power Domains
Esd-Robust I/O Driver Circuits
Latch-Up Robust Scr-Based Devices
Esd Protection Circuit
Integration of Memory, High Voltage and Logic Devices
Topology Density Aware Flow (Tdaf)
Deep Depleted Channel Mosfet with Minimized Dopant Fluctuation and Diffusion Levels
Latch-Up Free Esd Protection
Latch-Up Immune Esd Protection
Method for Forming Through Silicon via with Wafer Backside Protection
Method and Apparatus for Embedded Nvm Utilizing an Rmg Process
High Voltage Device
Integration of High Voltage Trench Transistor with Low Voltage Cmos Transistor
Fuse Sensing Circuits
Non-Volatile Memory Cell with High Bit Density
High Speed Low Power Fuse Circuit
Bonding Method Using Porosified Surfaces for Making Stacked Structures
Method for Forming a Pcram with Low Reset Current
Rram Structure with Improved Memory Margin
Patent:
8,536,558 →
Application:
13/562,646 →
Device with Integrated Power Supply
Stress Enhanced High Voltage Device
Mos with Recessed Lightly-Doped Drain
Novel Compact Charge Trap Multi-Time Programmable Memory
Latch-Up Robust Pnp-Triggered Scr-Based Devices
Litho Scanner Alignment Signal Improvement
Multi-Time Programmable Memory
Application:
13/589,176 →
Publication:
US 2014/0048867
Novel Latch-Up Immunity Nldmos
High Voltage Device
Fin-Type Memory
Self-Aligned Body Fully Isolated Device
Novel Rram Structure at Sti with Si-Based Selector
Method and Apparatus to Reduce Thermal Variations Within an Integrated Circuit Die Using Thermal Proximity Correction
Cd Control
High Gain Device
Integrated Circuit System with Sub-Geometry Removal and Method of Manufacture Thereof
Wrap Around Phase Change Memory
Esd Protection Circuit
Compact Rram Structure with Contact-Less Unit Cell
Compact Localized Rram Cell Structure Realized by Spacer Technology
Vertical Nanowire Based Hetero-Structure Split Gate Memory
Latch-Up Free Rc-Based Nmos Esd Power Clamp in Hv Use
High Noise Immunity with Latch-Up Free Esd Clamp
Floating Body Cell
Determination of Lithography Tool Process Condition
Filament Free Silicide Formation
Active Pad Patterns for Gate Alignment Marks
Tunneling Transistor
CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES
Dielectric Posts in Metal Layers
Esd Protection Circuit
Sandwich Damascene Resistor
Efficient Transfer of Materials Using Automated Guided Vehicles in Semiconductor Manufacturing
Integration of Germanium Photo Detector in Cmos Processing
High Voltage Finfet Structure
Sti Cmp Under Polish Monitoring
Field Effect Transistor with Self-Adjusting Threshold Voltage
Eeprom Cell
Eeprom Cell
Multi-Time Programmable Non-Volatile Memory
Patent:
8,772,108 →
Application:
13/775,844 →
Wafer Edge Protection
False-Triggered Immunity and Reliability-Free Esd Protection Device
Method of Forming Split-Gate Cell for Non-Volative Memory Devices
Fin Selector with Gated Rram
Resistive Non-Volatile Memory
Stackable Non-Volatile Memory
Esd Protection Circuit
Through Silicon Vias
Lateral Double-Diffused High Voltage Device
Method and Apparatus for Performing Optical Proximity and Photomask Correction
Integration of Low Rdson Ldmos with High Sheet Resistance Poly Resistor
Layout for Reticle and Wafer Scanning Electron Microscope Registration or Overlay Measurements
Etch Failure Prediction Based on Wafer Resist Top Loss
Cross Technology Reticle (Ctr) or Multi-Layer Reticle (Mlr) Cdu, Registration, and Overlay Techniques
Self-Aligned Contact for Replacement Metal Gate and Silicide Last Processes
Integrated Circuits with Laterally Diffused Metal Oxide Semiconductor Structures
Silicon-On-Insulator Integrated Circuits with Local Oxidation of Silicon and Methods for Fabricating the Same
Methods for Fabricating Integrated Circuits with the Implantation of Nitrogen
Transistor Devices Having an Anti-Fuse Configuration and Methods of Forming the Same
Non-Volatile Memory Device with Tsi/Tsv Application
Methods for Fabricating Integrated Circuits with the Implantation of Fluorine
An Integrated Circuit Comprising on-Chip Resistors with Plurality of First and Second Terminals Coupled to the Resistor Body
Reliable Interconnect for Semiconductor Device
Integrated Circuits Having Improved Split-Gate Nonvolatile Memory Devices and Methods for Fabrication of Same
Trench Transistor
Semiconductor Devices Including Photodetectors Integrated on Waveguides and Methods for Fabricating the Same
Finfet with Stressors
High Voltage Trench Transistor
Single Grooved Polishing Pad
Integrated Circuits Having Device Contacts and Methods for Fabricating the Same
Methods for Fabricating Integrated Circuits with a High-Voltage Mosfet
Mapping a Lookup Table to Prefabricated Tcams
Esd Protection Circuit
Esd Protection Circuit
Reliable Contacts
Imaging Methods
Patent:
8,816,278 →
Application:
14/019,280 →
Dielectric Stack
Efficient Integration of Cmos with Poly Resistor
Method for Forming N-Shaped Bottom Stress Liner
Reliable Contacts
Methods for Converting Planar Designs to Finfet Designs in the Design and Fabrication of Integrated Circuits
Semiconductor Devices Including Avalanche Photodetector Diodes Integrated on Waveguides and Methods for Fabricating the Same
Methods for Forming Thin Film Storage Memory Cells
Patent:
8,895,397 →
Application:
14/054,084 →
High Ion and Low Sub-Threshold Swing Tunneling Transistor
Cmp Head Structure
Cmp Head Structure
Monitoring Pattern for Devices
High Rectifying Ratio Diode
Setup for Multiple Cross-Section Sample Preparation
Rram Cell with Bottom Electrode(S) Positioned in a Semiconductor Substrate
Methods for Fabricating Integrated Circuits Using Chemical Mechanical Polishing
Reliable Interconnect for Semiconductor Device
Laser-Enhanced Chemical Etching of Nanotips
Tsv Without Zero Alignment Marks
Methods of Forming Replacement Gate Structures for Semiconductor Devices and the Resulting Semiconductor Products
Methods and Media for Lot Dispatch Priority
Semiconductor Wafers Employing a Fixed-Coordinate Metrology Scheme and Methods for Fabricating Integrated Circuits Using the Same
Integrated Circuits with Copper Hillock-Detecting Structures and Methods for Detecting Copper Hillocks Using the Same
Three-Dimensional Integrated Circuit Structures Providing Thermoelectric Cooling and Methods for Cooling Such Integrated Circuit Structures
Nonvolative Memory with Filament
Integrated Circuits Including a Resistance Element and Gate-Last Techniques for Forming the Integrated Circuits
Multi-Level Memory Cells and Methods for Forming Multi-Level Memory Cells
Three-Dimensional Non-Volatile Memory
System and Methods for Opc Model Accuracy Management and Disposition
Back-Gated Non-Volatile Memory Cell
Efficient Optical Proximity Correction Repair Flow Method and Apparatus
Surface Topography Enhanced Pattern (Step) Matching
Nonvolative Memory
Device with Isolation Buffer
1T Sram/Dram
Control Gate
Split Gate Embedded Memory Technology and Manufacturing Method Thereof
Deep Depleted Channel Mosfet with Minimized Dopant Fluctuation and Diffusion Levels
Novel Rram Structure at Sti with Si-Based Selector
Recessing and Capping of Gate Structures with Varying Metal Compositions
Middle in-Situ Doped Sige Junctions for Pmos Devices on 28 Nm Low Power/High Performance Technologies Using a Silicon Oxide Encapsulation, Early Halo and Extension Implantations
Wafer Stack Protection Seal
Scalable and Reliable Non-Volatile Memory Cell
Design-For-Manufacturing - Design-Enabled-Manufacturing (Dfm-Dem) Proactive Integrated Manufacturing Flow
Integrated Circuits with Stressed Semiconductor-on-Insulator (Soi) Body Contacts and Methods for Fabricating the Same
Silicon-On-Insulator Integrated Circuit Devices with Body Contact Structures
Cmp Wafer Edge Control of Dielectric
Simple and Cost-Free Mtp Structure
Methods for Fabricating Integrated Circuits and Components Thereof
Integrated Circuits Having Nickel Silicide Contacts and Methods for Fabricating the Same
Equivalent Fuse Circuit for a One-Time Programmable Read-Only Memory Array
Topography Driven Opc and Lithography Flow
Methods for Fabricating Integrated Circuits with Spin Torque Transfer Magnetic Random Access Memory (Stt-Mram) Including a Passivation Layer Formed Along Lateral Sidewalls of a Magnetic Tunnel Junction of the Stt-Mram
Ldmos with Improved Breakdown Voltage
Method of Forming a 1-Bits-Per-Cell or 2-Bits-Per-Cell Thyristor-Based Memory Structure
Application:
14/277,068 →
Publication:
US 2015/0333068
Vertical Random Access Memory with Selectors
Integrated Circuits with Laterally Diffused Metal Oxide Semiconductor Structures and Methods for Fabricating the Same
Formation of the Dielectric Cap Layer for a Replacement Gate Structure
Bandgap Reference Voltage Generator Circuits
Integrated Circuits with Hall Effect Sensors and Methods for Producing Such Integrated Circuits
Systems and Methods for Testing Performance of Memory Modules
Non-Volatile Memory Cell Arrays and Methods of Fabricating Semiconductor Devices
Patent:
9,165,610 →
Application:
14/318,766 →
Method for Forming a Pcram with Low Reset Current
Mos with Recessed Lightly-Doped Drain
Novel Method to Tune Narrow Width Effect with Raised S/D Structure
3D High Voltage Charge Pump
High Voltage Device
Resistive Memory Device
Integrated Circuits with Memory Cells and Methods of Manufacturing the Same
Patent:
9,209,275 →
Application:
14/445,279 →
Methods for Fabricating Integrated Circuits Having Device Contacts
Structure and Metohds of Improving Reliability of Non-Volatile Memory Devices
Metallization Layers Configured for Reduced Parasitic Capacitance
Patent:
9,230,913 →
Application:
14/457,155 →
Split Gate Embedded Memory Technology and Method of Manufacturing Thereof
Integrated Circuits with Finfet Nonvolatile Memory
Silicon-On-Insulator Integrated Circuit Devices with Body Contact Structures and Methods for Fabricating the Same
Selector-Resistive Random Access Memory Cell
Magnetic Memory Device and Method of Forming Thereof
Cd Control
Guard Ring for Memory Array
Contact Strap for Memory Array
High Voltage Device
Grounding of Silicon-on-Insulator Structure
Integrated Circuit Structures with Spin Torque Transfer Magnetic Random Access Memory and Methods for Fabricating the Same
Integrated Circuits with Laterally Diffused Metal Oxide Semiconductor Structures and Methods for Fabricating the Same
Simple and Cost-Free Mtp Structure
Planar Passivation for Pads
Method and Apparatus for Bitcell Modeling
Arc Residue-Free Etching
Integrated Circuits Including Magnetic Core Inductors and Methods for Fabricating the Same
Integrated Circuit Structures with Spin Torque Transfer Magnetic Random Access Memory Ultilizing Aluminum Metallization Layers and Methods for Fabricating the Same
Integrated Circuit Structures with Spin Torque Transfer Magnetic Random Access Memory Having Increased Memory Cell Density and Methods for Fabricating the Same
Test Structure for Monitoring Liner Oxidation
Methods for Fabricating Integrated Circuits with Improved Active Regions
Method for Forming an Air Gap Around a Through-Silicon Via
Finfet
Pellicles and Devices Comprising a Photomask and the Pellicle
Reliable Non-Volatile Memory Device
Two-Bits Per Cell Structure with Spin Torque Transfer Magnetic Random Access Memory and Methods for Fabricating the Same
Patent:
9,263,665 →
Application:
14/565,536 →
Memory Cell with Decoupled Channels
Integrated Circuits Having Improved Split-Gate Nonvolatile Memory Devices and Methods for Fabrication of Same
Methods for Fabricating Flash Memory Cells and Integrated Circuits Having Flash Memory Cells Embedded with Logic
Patent:
9,343,466 →
Application:
14/584,973 →
Dual Encapsulation Integration Scheme for Fabricating Integrated Circuits with Magnetic Random Access Memory Structures
Integrated Circuits, Methods of Forming the Same, and Methods of Determining Gate Dielectric Layer Electrical Thickness in Integrated Circuits
Low Voltage Semiconductor Memory Device and Method of Operation
Bonding Method Using Porosified Surfaces for Making Stacked Structures
Wrap Around Phase Change Memory
Hybrid Tsv and Method for Forming the Same
Compact Localized Rram Cell Structure Realized by Spacer Technology
Sandwich Damascene Resistor
Methods for Fabricating Device Substrates and Integrated Circuits
Patent:
9,390,962 →
Application:
14/639,645 →
Method of Forming a via Contact
Edge Structure for Backgrinding Asymmetrical Bonded Wafer
A High Voltage Device
Integrated Circuits Using Silicon on Insulator Substrates and Methods of Manufacturing the Same
Integrated Circuits with Memory Cells and Methods of Manufacturing the Same
Programmable Active Cooling Device
Simple and Cost-Free Mtp Structure
Simple and Cost-Free Mtp Structure
Simple and Cost-Free Mtp Structure
Fin Selector with Gated Rram
High Voltage Trench Transistor
Novel Latch-Up Immunity Nldmos
Low Power Memory Cell with High Sensing Margin
One Quarter Wavelength Transmission Line Based Electrostatic Discharge (Esd) Protection for Integrated Circuits
Methods for Fabricating Integrated Circuits with a High-Voltage Mosfet
Ldmos with Improved Breakdown Voltage and with Non-Uniformed Gate Dielectric and Gate Electrode
Interposers for Integrated Circuits with Multiple-Time Programming and Methods for Manufacturing the Same
Interposers for Integrated Circuits with One-Time Programming and Methods for Manufacturing the Same
Application:
14/719,499 →
Publication:
US 2016/0343719
Small Pitch and High Density Contact Array
System and Methods for Opc Model Accuracy Management and Disposition
Method of Forming Split-Gate Cell for Non-Volative Memory Devices
Pattern Classification Based Proximity Corrections for Reticle Fabrication
Creation of Wide Band Gap Material for Integration to Soi Thereof
Semiconductor Device Including an N-Well Structure
Methods for Producing Integrated Circuits with Interposers and Integrated Circuits Produced from Such Methods
Integrated Circuits Having Copper Bonding Structures with Silicon Carbon Nitride Passivation Layers Thereon and Methods for Fabricating Same
Defect Isolation Methods and Systems
Integrated Mems-Cmos Devices and Methods for Fabricating Mems Devices and Cmos Devices
Patent:
9,546,090 →
Application:
14/826,449 →
Photonic Devices with Through Dielectric via Interposer
Application:
14/830,743 →
Publication:
US 2017/0054039
Integrated Mems Pressure Sensor and Mems Inertial Sensor
Patent:
9,550,668 →
Application:
14/834,498 →
Rc-Stacked Mosfet Circuit for High Voltage (Hv) Electrostatic Discharge (Esd) Protection
Integrated Circuits Having Tunnel Transistors and Methods for Fabricating the Same
Gate-Grounded Metal Oxide Semiconductor Device
High Gain Device
High Voltage Transistor
Non-Volatile Resistive Random Access Memory Crossbar Devices with Maximized Memory Element Density and Methods of Forming the Same
Magnetic Tunnel Junction Stack Alignment Scheme
Integrated Inductor and Magnetic Random Access Memory Device
Patent:
9,397,139 →
Application:
14/862,174 →
Digital Phase Locked Loop (Pll) System and Method with Phase Tracing
Patent:
9,548,748 →
Application:
14/867,289 →
Digitally Controlled Oscillator (Dco) for a Phase Locked Loop (Pll) System
Patent:
9,559,709 →
Application:
14/867,298 →
Integrated Circuits with Alignment Marks and Methods of Producing the Same
Plasma Discharge Path
Integrated Circuits with Contacts Through a Buried Oxide Layer and Methods of Producing the Same
Patent:
9,472,512 →
Application:
14/883,100 →
Low Power Embedded One-Time Programmable (Otp) Structures
Energy Efficient Three-Terminal Voltage Controlled Memory Cell
Integrated Circuits Having an Anti-Fuse Device and Methods of Forming the Same
Integrated Circuits Having Multiple Gate Devices with Dual Threshold Voltages and Methods for Fabricating Such Integrated Circuits
High Voltage Device with Low Rdson
Devices with Embedded Non-Volatile Memory and Metal Gates and Methods for Fabricating the Same
Patent:
9,583,499 →
Application:
14/952,536 →
P-Channel Multi-Time Programmable (Mtp) Memory Cells
Crack Stop Layer in Inter Metal Layers
Application:
14/956,401 →
Publication:
US 2017/0162501
Digital Phase Locked Loop (Pll) System with Frequency Band Jump in Lock Mode
Patent:
9,520,885 →
Application:
14/958,330 →
System and Method for Modular Simulation of Spin Transfer Torque Magnetic Random Access Memory Devices
Semiconductor Devices with Cavities and Methods for Fabricating Semiconductor Devices with Cavities
Device Without Zero Mark Layer
Semiconductor Device with Improved Narrow Width Effect and Method of Making Thereof
Self-Aligned High Voltage Ldmos
Electronic Devices Including Substantially Hermetically Sealed Cavities and Getter Films with Kelvin Measurement Arrangement for Evaluating the Getter Films and Methods for Fabricating the Same
Methods for Evaluating Semiconductor Device Structures
Patent:
9,613,874 →
Application:
14/985,178 →
Integrated Led and Led Driver Units and Methods for Fabricating the Same
Drive Current Enhancement for Integrated Circuit Memory Structures
Patent:
9,583,168 →
Application:
14/985,244 →
Integrated Circuits with Aluminum via Structures and Methods for Fabricating the Same
Low Cost High Performance Eeprom Device
Patent:
9,659,947 →
Application:
14/985,450 →
High Voltage Device with Low Rdson
Ultra Low Voltage Ring Oscillator with Redundant Inverter
Integrated Circuits with Gaps
Integrated Circuits with Electrostatic Discharge Protection
Cmp Head Structure with Retaining Ring
Cmp Head Structure with Retaining Ring
High Sensing Margin Magnetic Resistive Memory Device in Which a Memory Cell Read and Write Select Transistors to Provide Different Read and Write Paths
Voltage Controlled Spin Switches for Low Power Applications
Magnetic Memory Cells with Fast Read/Write Speed
Mram with Metal-Insulator-Transition Material
Magnetic Memory Cells with Low Switching Current Density
Magnetic Memory Cells with High Write Current and Read Stability
Split Gate Embedded Memory Technology and Method of Manufacturing Thereof
Three-Axis Monolithic Mems Accelerometers and Methods for Fabricating Same
Selector Device for a Non-Volatile Memory Cell
High Density Multi-Time Programmable Resistive Memory Devices and Method of Forming Thereof
Defect Isolation Methods and Systems
Integration of Spintronic Devices with Memory Device
Cross Technology Reticle (Ctr) or Multi-Layer Reticle (Mlr) Cdu, Registration, and Overlay Techniques
Silicon Controlled Rectifier (Scr) Based Esd Protection Device
Magnetic Memory with High Thermal Budget
Magnetic Memory with High Thermal Budget
Magnetic Memory with Tunneling Magnetoresistance Enhanced Spacer Layer
Magnetic Memory with Tunneling Magnetoresistance Enhanced Spacer Layer
Through Silicon Vias
Integrated Magnetic Random Access Memory with Logic Device Having Low-K Interconnects
Programmable Integrated Circuits and Methods of Forming the Same
Patent:
9,659,943 →
Application:
15/063,963 →
High Thermal Budget Magnetic Memory
Voltage-Tunable Magnetic Devices for Communication Applications
Bottom Electrode for Magnetic Memory to Increase Tmr and Thermal Budget
Application:
15/075,222 →
Publication:
US 2016/0276580
Magnetic Shielding of Mram Package
Mram Chip Magnetic Shielding
Storage Layer for Magnetic Memory with High Thermal Stability
Methods for Evaluating Strain of Crystalline Devices
Patent:
9,581,506 →
Application:
15/084,834 →
Domain Wall Magnetic Memory
Methods for Fabricating Integrated Circuits with Low, Medium, and/or High Voltage Transistors on an Extremely Thin Silicon-on-Insulator Substrate
Patent:
9,653,365 →
Application:
15/093,888 →
Integrated Circuits Resistant to Electrostatic Discharge and Methods for Producing the Same
Patent:
9,741,849 →
Application:
15/094,635 →
STT-MRAM Bitcell for Embedded Flash Applications
Integrated Circuit Electrostatic Discharge Protection
Integrated Circuits with Lateral Bipolar Transistors and Methods for Fabricating the Same
Patent:
9,761,664 →
Application:
15/133,488 →
Integrated Circuits with Optical Modulators and Photodetectors and Methods for Producing the Same
Patent:
9,711,662 →
Application:
15/134,542 →
Integrated Circuit Electrostatic Discharge Protection
Integrated Circuits with Selectively Strained Device Regions and Methods for Fabricating Same
Integrated Circuits Having Shielded Mems Devices and Methods for Fabricating Shielded Mems Devices
Compact Rram Structure with Contact-Less Unit Cell
Integrated Circuits with Deep and Ultra Shallow Trench Isolations and Methods for Fabricating the Same
Extended Drain Metal-Oxide-Semiconductor Transistor
Magnetic Shielding for Mtj Device or Bit
Integrated Magnetic Random Access Memory with Logic Device
Magnetic Tunnel Junction Element
High Gain Transistor for Analog Applications
Integrated Circuits with Capacitors and Methods for Producing the Same
Patent:
9,646,963 →
Application:
15/181,446 →
Integrated Circuits Including Ldmos Transistor Structures and Methods for Fabricating Ldmos Transistor Structures
Patent:
9,793,394 →
Application:
15/181,780 →
Vertical Random Access Memory with Selectors
Mems Device for Harvesting Sound Energy and Methods for Fabricating Same
Fin-Based Nonvolatile Memory Structures, Integrated Circuits with Such Structures, and Methods for Fabricating Same
Integrated Circuits with Programmable Memory and Methods for Producing the Same
Wafer Stack Protection Seal
Wide Range Level Shifter for Low Voltage Input Applications
Patent:
9,843,326 →
Application:
15/227,979 →
Integrated Circuits and Methods for Fabricating Integrated Circuits and Electrical Interconnects for Iii-V Semiconductor Devices
Extended Drain Metal-Oxide-Semiconductor Transistor
Patent:
9,871,132 →
Application:
15/236,494 →
Mram Magnetic Shielding with Fan-Out Wafer Level Packaging
Integrated Two-Terminal Device and Logic Device with Compact Interconnects Having Shallow via for Embedded Application
Fabrication Methods for a Piezoelectric Micro-Electromechanical System (Mems)
3D Mram with Through Silicon Vias or Through Silicon Trenches Magnetic Shielding
Mos Varactors and Methods for Fabricating Mos Varactors
Integrated Circuits Including a Dummy Metal Feature and Methods of Forming the Same
Vdmos Transistors, Bcd Devices Including Vdmos Transistors, and Methods for Fabricating Integrated Circuits with Such Devices
Multi-Time Programmable (Mtp) Memory Cells, Integrated Circuits Including the Same, and Methods for Fabricating the Same
Application:
15/267,664 →
Publication:
US 2018/0083008
Integrated Circuit Electrostatic Discharge Protection with Disable-Enable
Application:
15/268,703 →
Publication:
US 2018/0083440
Integrated Circuits with High Voltage Devices and Methods for Producing the Same
Integrated Circuits with Flash Memory and Methods for Producing the Same
Patent:
9,780,231 →
Application:
15/271,528 →
Integrated Circuits Having Transistors with High Holding Voltage and Methods of Producing the Same
Integrated Circuits with Deep Trench Isolations and Methods for Producing the Same
Patent:
9,831,304 →
Application:
15/271,599 →
Method for producing integrated circuit memory cells with less dedicated lithographic steps
Semiconductor Chips with Seal Rings and Electronic Test Structures, Semiconductor Wafers Including the Semiconductor Chips, and Methods for Fabricating the Same
Patent:
9,728,474 →
Application:
15/278,257 →
ELECTRODE ARRANGEMENT FOR A pMUT and pMUT TRANSDUCER ARRAY
Integrated Iii-V Device and Driver Device Units and Methods for Fabricating the Same
High Density Cross Point Resistive Memory Structures and Methods for Fabricating the Same
Reliable Non-Volatile Memory Device
Magnetism-Controllable Dummy Structures in Memory Device
Spacer Layer for Magnetoresistive Memory
System for Detection of a Photon Emission Generated by a Device and Methods for Detecting the Same
Capacitor Structure
Tunneling Field Effect Transistor
Integrated Circuits and Methods for Fabricating Integrated Circuits with Non-Volatile Memory Structures
Patent:
9,825,185 →
Application:
15/383,048 →
Integrated Circuits with Sram Devices Having Read Assist Circuits and Methods for Operating Such Circuits
Integrated Circuits and Methods for Fabricating Integrated Circuits with Magnetic Tunnel Junction (Mtj) Structures
Application:
15/383,122 →
Publication:
US 2018/0175284
Integrated Circuits with Programmable Memory Cells and Methods for Programming the Same
Patent:
9,799,387 →
Application:
15/386,200 →
Integrated Circuits Including Magnetic Random Access Memory Structures and Methods for Fabricating the Same
Application:
15/392,262 →
Publication:
US 2018/0182809
Integrated Two-Terminal Device with Logic Device for Embedded Application
Integrated Circuits and Coupled Inductors with Isotropic Magnetic Cores, and Methods for Fabricating the Same
Patent:
9,966,186 →
Application:
15/394,212 →
Methods for Removal of Hard Mask
Transistor with Source-Drain Silicide Pullback
Hall Element for 3-D Sensing and Method for Producing the Same
Integrated Mems-Cmos Devices and Integrated Circuits with Mems Devices and Cmos Devices
Application:
15/405,911 →
Publication:
US 2017/0121172
Integrated Circuits with Magnetic Tunnel Junctions and Methods for Producing the Same
Patent:
9,865,801 →
Application:
15/410,088 →
Method for Manufacturing a Compact Otp/Mtp Technology
Reliable Pad Interconnects
Reliable Passivation for Integrated Circuits
Compact and Reliable Changeable Negative Voltage Transmission Circuit
Method and System for Detecting a Coolant Leak in a Dry Process Chamber Wafer Chuck
Device Alignment Mark Using a Planarization Process
Application:
15/432,933 →
Publication:
US 2018/0233661
Embedded Memory in Back-End-of-Line Low-K Dielectric
Patent:
10,008,387 →
Application:
15/432,941 →
Strap Layout for Non-Volatile Memory Device
Seal Ring for Wafer Level Package
Integrated Circuits with Magnetic Tunnel Junctions and Methods for Producing the Same
Application:
15/443,741 →
Publication:
US 2017/0309813
Integrated Circuits with Magnetic Tunnel Junctions and Methods for Producing the Same
Mram Memory Device and Manufacturing Method Thereof
Patent:
9,997,562 →
Application:
15/458,944 →
Integrated Circuits with High Voltage Transistors and Methods for Producing the Same
Patent:
10,032,905 →
Application:
15/468,188 →
Integrated Hall Effect Sensors with Voltage Controllable Sensitivity
Application:
15/470,936 →
Publication:
US 2017/0288131
Integrated Circuits with Capacitors and Methods for Producing the Same
Integrated Circuits with Capacitors and Methods for Producing the Same
Electronic Devices with Tunable Electrostatic Discharge Protection and Methods for Producing the Same
Patent:
10,032,761 →
Application:
15/481,835 →
Method to Form Thicker Erase Gate Poly Superflash Nvm
Patent:
10,020,372 →
Application:
15/496,752 →
Integrated Circuits with Electrostatic Discharge Protection and Methods for Producing the Same
Patent:
10,032,765 →
Application:
15/598,764 →
Low Cost High Performance Eeprom Device
Top Electrode Dome Formation
Patent:
9,905,282 →
Application:
15/608,407 →
Methods for Fabricating Integrated Circuits Including Substrate Contacts
Patent:
9,997,393 →
Application:
15/616,143 →
Methods for Fabricating Electronic Devices Including Substantially Hermetically Sealed Cavities and Getter Films
High Voltage Device with Low Rdson
Heat Dissipation & Series Resistance Reduction of Pa & Rf Switch in Slt by Backside Thick Metal
Patent:
9,960,115 →
Application:
15/640,928 →
Creation of Wide Band Gap Material for Integration to Soi Thereof
Resistive Memory Device
Low Power Embedded One-Time Programmable (Otp) Structures
Hall Element for 3-D Sensing Using Integrated Planar and Vertical Elements and Method for Producing the Same
Patent:
10,050,082 →
Application:
15/678,740 →
High Voltage Pnp Using Isolation for Esd and Method for Producing the Same
Patent:
10,037,988 →
Application:
15/685,798 →
High Density Multi-Time Programmable Resistive Memory Devices and Method of Forming Thereof
Device Without Zero Mark Layer
Fin Selector with Gated Rram
Ldmos Transistor Structures and Integrated Circuits Including Ldmos Transistor Structures
Magnetic Tunnel Junction Element with Reduced Temperature Sensitivity
Application:
15/803,874 →
Publication:
US 2018/0130943
Multi-Time Programmable Device
Extended Drain Metal-Oxide-Semiconductor Transistor
Semiconductor Devices with Cavities and Methods for Fabricating Semiconductor Devices with Cavities
Application:
15/899,785 →
Publication:
US 2018/0170748
Integrated Circuits and Coupled Inductors with Isotropic Magnetic Cores, and Methods for Fabricating the Same
Integrated Magnetic Random Access Memory with Logic Device Having Low-K Interconnects
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Release of Security Interest
Nov 18, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054475/0718 →
Release of Security Interest
Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
Assignment of Assignor's Interest
Nov 19, 2020
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 054600/0031 →