Method for manufacturing a compact OTP/MTP technology
View Patent ↗Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate.
1. A method comprising:
providing a substrate having a buried oxide (BOX) layer formed over the substrate;
forming first and second fins on the BOX layer, wherein the second fin is arranged opposite the first fin on the BOX layer such that an end of the second fin is aligned to an end of the first fin with a gap in between;
forming first and second gates, laterally separated, over and perpendicular to the first and second fins, respectively;
forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of the first fin, the second fin, or both fins;
forming at least one additional pair of separated first and second fins parallel to and vertically spaced from the first and second fins;
extending the first and second gates over one or more of the additional first and second fins, respectively;
forming a source/drain (S/D) region in each of the first and second fins adjacent to the first and second gates, respectively, remote from the at least one third gate;
utilizing each of the first and second gates as a word line (WL);
utilizing each at least one third gate as a source line (SL) or connecting a SL to the S/D region; and
connecting a bit line (BL) to the S/D region or the at least one third gate.
2. The method according to claim 1 , wherein the at least one third gate comprises two third gates separated from each other.
3. The method according to claim 2 , comprising:
forming an L-shaped liner on each sidewall of each first, second, and third gate;
forming a first spacer on each L-shaped liner of the first and second gates; and
forming a second spacer on each L-shaped liner of each third gate.
4. The method according to claim 3 , comprising:
separating the second spacers from the first spacers; and
forming source/drain regions between each third gate and the adjacent first and second gates.
5. The method according to claim 3 , comprising forming the first and second spacers with no gap in between.
6. The method according to claim 1 , wherein the at least one third gate comprises a single merged gate filling the gap and overlapping an end of each of the first and second fins.
7. The method according to claim 1 , further comprising:
extending the at least one third gate over the one or more additional pairs of first and second fins.
8. The method according to claim 1 , further comprising:
forming an additional at least one third gate over each of the one or more additional pairs of first and second fins.
9. A device comprising:
a substrate having a buried oxide (BOX) layer formed over the substrate;
first and second fins formed on the BOX layer, wherein the second fin is arranged opposite the first fin on the BOX layer such that an end of the second fin is aligned to an end of the first fin with a gap in between;
first and second gates, laterally separated, formed over and perpendicular to the first and second fins, respectively;
at least one third gate formed between the first and second gates on the BOX layer through the gap, each third gate overlapping an end of the first fin, the second fin, or both fins;
at least one additional pair of separated first and second fins formed parallel to and vertically spaced from the first and second fins, wherein the first and second gates extend over one or more of the additional first and second fins, respectively;
a source/drain (S/D) region formed in each of the first and second fins adjacent to the first and second gates, respectively, remote from the at least one third gate; and
a bit line (BL) connected to the S/D region or the third gate.
10. The device according to claim 9 , wherein each of the first and second gates are utilized as a word line (WL) and each third gate is utilized as a source line (SL) or a SL is connected to the S/D region.
11. The device according to claim 9 , wherein the at least one third gate comprises two third gates separated from each other.
12. The device according to claim 11 , further comprising:
an L-shaped liner on each sidewall of each first, second, and third gate;
a first spacer on each L-shaped liner of the first and second gates; and
a second spacer on each L-shaped liner of each third gate.
13. The device according to claim 12 , wherein the second spacers are separated from the first spacers, the device further comprising source/drain regions formed between each third gate and the adjacent first and second gates.
14. The device according to claim 12 , wherein the first and second spacers are formed with no gap in between.
15. The device according to claim 9 , wherein the at least one third gate comprises a single merged gate filling the gap and overlapping an end of each of the first and second fins.
16. The device according to claim 9 , further comprising the at least one third gate extending over the one or more additional pairs of first and second fins.
17. The device according to claim 9 , further comprising an additional at least one third gate over each of the one or more additional pairs of first and second fins.