Methods for fabricating integrated circuits with a high-voltage MOSFET

1. A method for fabricating an integrated circuit comprising:

forming a first silicon material layer over a semiconductor substrate, the semiconductor substrate including a high-voltage MOSFET region, a logic device region, and a memory array region, the memory array region having formed on the semiconductor substrate a memory gate stack;

forming a first capping layer over the first silicon material layer and over the memory gate stack;

removing the first capping layer from over the memory array region but not from over the high-voltage MOSFET region and the logic device region of the integrated circuit;

forming a second silicon material layer over the first capping layer and over the first silicon material layer;

removing the second silicon material layer in an amount such that the second silicon material layer is completely removed from over the high-voltage MOSFET region and the logic device region;

removing the first capping layer from over the first silicon material layer in the high-voltage MOSFET region and the logic device region;

forming a second capping layer over the first silicon material layer in the high-voltage MOSFET region and the logic device region;

removing the first silicon material layer and the second capping layer from the high-voltage MOSFET region except in an area overlying a channel region of the high-voltage MOSFET region;

forming a photoresist material layer over the memory array region and the logic device region; and

exposing the semiconductor substrate to a dopant ion implantation process.

2. The method of claim 1 , wherein forming the first capping layer comprises depositing a silicon oxide capping layer.

3. The method of claim 1 , further comprising removing the first silicon material layer and the second capping layer from a word-line region of the memory array region.

4. The method of claim 3 , further comprising removing the first silicon material layer and the second capping layer from the logic device region except in an area overlying a channel region of the logic device region.

5. The method of claim 1 , wherein removing the first capping layer comprises removing the first capping layer using a wet etching process.

6. The method of claim 1 , wherein exposing the semiconductor substrate to the dopant ion implantation process comprises forming a lightly-doped drain (LDD) region in the high-voltage MOSFET region.

7. The method of claim 1 , wherein forming the first silicon material layer over the semiconductor substrate comprises forming the first silicon material layer over a semiconductor substrate that comprises a floating-gate memory gate stack.

8. The method of claim 1 , wherein forming the first silicon material layer comprises depositing a polysilicon layer.

9. The method of claim 1 , wherein forming the second silicon material layer comprises forming a dummy polysilicon layer.

10. The method of claim 1 , wherein removing the second silicon material layer comprises removing the second silicon material layer using chemical mechanical planarization.

11. The method of claim 10 , wherein removing the second silicon material layer further comprises removing the second silicon material layer using an etching process.

12. A method for fabricating an integrated circuit comprising:

forming a first silicon material layer over a semiconductor substrate, the semiconductor substrate including a high-voltage MOSFET region, a logic device region, and a memory array region, the memory array region having formed on the semiconductor substrate a memory gate stack;

forming a first capping layer over the first silicon material layer and over the memory gate stack;

removing the first capping layer from over the memory array region but not from over the high-voltage MOSFET region and the logic device region of the integrated circuit;

forming a second silicon material layer over the first capping layer and over the first silicon material layer;

removing the second silicon material layer in an amount such that the second silicon material layer is completely removed from over the high-voltage MOSFET region and the logic device region;

removing the first capping layer from over the first silicon material layer in the high-voltage MOSFET region and the logic device region;

forming a second capping layer over the first silicon material layer in the high-voltage MOSFET region and the logic device region;

removing the first silicon material layer and the second capping layer from the high-voltage MOSFET region except in an area overlying a channel region of the high-voltage MOSFET region.

13. The method of claim 12 , wherein forming the first capping layer comprises depositing a silicon oxide capping layer.

14. The method of claim 12 , further comprising removing the first silicon material layer and the second capping layer from a word-line region of the memory array region.

15. The method of claim 14 , further comprising removing the first silicon material layer and the second capping layer from the logic device region except in an area overlying a channel region of the logic device region.

16. The method of claim 12 , wherein removing the first capping layer comprises removing the first capping layer using a wet etching process.

17. The method of claim 12 , wherein exposing the semiconductor substrate to the dopant ion implantation process comprises forming a lightly-doped drain (LDD) region in the high-voltage MOSFET region.

18. The method of claim 12 , wherein forming the first silicon material layer over the semiconductor substrate comprises forming the first silicon material layer over a semiconductor substrate that comprises a floating-gate memory gate stack.

19. The method of claim 12 , wherein forming the first silicon material layer comprises depositing a polysilicon layer.

20. A method for fabricating an integrated circuit comprising:

depositing a first polysilicon layer over a semiconductor substrate, the semiconductor substrate including a high-voltage MOSFET region, a logic device region, and a memory array region, the memory array region having formed on the semiconductor substrate a floating-gate memory stack;

depositing a silicon oxide first capping layer over the first polysilicon layer and over the memory gate stack;

removing the first capping layer from over the memory array region but not from over the high-voltage MOSFET region and the logic device region of the integrated circuit;

depositing a second polysilicon layer over the first capping layer and over the first polysilicon layer;

removing, by a combination of chemical mechanical planarization and etching, the second polysilicon layer in an amount such that the second silicon material layer is completely removed from over the high-voltage MOSFET region and the logic device region;

forming a second capping layer over the first silicon material layer in the high-voltage MOSFET region and the logic device region;

removing the first silicon material layer and the second capping layer from the high-voltage MOSFET region except in an area overlying a channel region of the high-voltage MOSFET region;

removing the first silicon material layer and the second capping layer from a word-line region of the memory array region;

removing the first silicon material layer and the second capping layer from the logic device region except in an area overlying a channel region of the logic device region;

depositing a photoresist material layer over the memory array region and the logic device region; and

forming a lightly-doped drain (LDD) region in the high-voltage MOSFET region by exposing the semiconductor substrate to a dopant ion implantation process.