Latch-up free RC-based NMOS ESD power clamp in HV use

1. A device comprising:

a protection circuit for a plurality of voltage supply terminals, the protection circuit comprising:

a resistor and a capacitor connected in series across a pair of the supply terminals;

an NMOSFET having a gate coupled by a body resistance to one of the supply terminals;

an external resistor connected in series with the NMOSFET across the supply terminals; wherein:

the gate of the NMOSFET is coupled to a junction between the resistor and capacitor;

a plurality of diodes is connected in series between the gate of the NMOSFET and the junction; and

a first diode is connected at its input to the junction and its output is coupled to a junction between the NMOSFET and the external resistor.

2. The device according to claim 1 , wherein the first diode is connected in series with second and third diodes.

3. The device according to claim 1 , further comprising a switch connected between the output of the first diode and the junction between the NMOSFET and the external resistor.

4. The device according to claim 3 , wherein the switch comprises a latch circuit.

5. The device according to claim 4 , wherein the output of the first diode is connected to an input of a second diode, and wherein the input of the second diode and an output of the second diode is connected respectively, to first and second control terminals of the latch circuit.

6. The device according to claim 5 , wherein a third diode is connected between the second diode and the gate of the NMOSFET.

7. The device according to claim 1 , wherein the resistance value of the external resistor is set to a value to extend a snapback trigger voltage range of the device.

8. A method for protecting an integrated circuit against electrostatic discharge damage, the method comprising:

connecting a resistor and capacitor in series across a pair of the supply terminals;

coupling a gate of a NMOSFET by a body resistance to one of the supply terminals;

connecting an external resistor in series with the NMOSFET across the supply terminals;

coupling the gate of the NMOSFET to a junction between the resistor and capacitor;

connecting a plurality of diodes connected in series between the gate of the NMOSFET and a junction with the capacitor; and

connecting a switch between the output of one of the diodes and a junction between the NMOSFET and the external resistor.

9. A method as recited in claim 8 , wherein the switch comprises a latch circuit.

10. A method as recited in claim 9 , wherein the output of the first diode is connected to an input of a second diode, and wherein an input and an output of a second diode is connected respectively, to first and second control terminals of the latch circuit.

11. A method for protecting an integrated circuit against electrostatic discharge damage, the method comprising:

connecting a resistor and a capacitor in series across a pair of the supply terminals;

coupling a gate of a NMOSFET by a body resistance to one of the supply terminals;

connecting an external resistor in series with the NMOSFET across the supply terminals;

coupling the gate of the NMOSFET to a junction between the resistor and capacitor;

and setting the resistance value of the external resistor to a value to extend a snapback trigger voltage range.

12. A method for extending snapback behavior of an RC-based electrostatic discharge protection device comprising:

providing a first current discharge path between supply terminals during an electrostatic discharge event; and

providing a second current discharge path in parallel with the first discharge path;

wherein:

a snapback trigger voltage range of the protection device is extended;

the first current discharge path comprises body resistance of the protection device and the second current discharge path comprises an external resistor; and

a plurality of diodes are connected in series between the gate of an NMOSFET and a capacitor; and

a switch is coupled between the output of one of the diodes and a junction between the NMOSFET and the external resistor.

13. A method as recited in claim 12 , wherein the switch comprises a latch.