Method and system for introducing physical damage into an integrated circuit device for verifying testing program and its results
View Patent ↗According to an embodiment of the disclosure, a method verifies bitmap information or test data information for a semiconductor device. The method places a defect on a semiconductor device at an actual defect location using a laser to physically damage the semiconductor device. A logical address associated with the defect is detected and bitmap information or test data information is reviewed to determine an expected location corresponding to the logical address. Then, the accuracy of the bitmap information or the test data information is determined by comparing the actual defect location with the expected location. A deviation between the two indicates an inaccuracy.
1. A method of verifying bitmap information or test data information for a semiconductor device, the method comprising:
placing a defect on a semiconductor device at an actual defect location by physically damaging the semiconductor device with a laser at the actual defect location;
detecting the defect at a logical address;
reviewing at least one of bitmap information or test data information to determine an expected location corresponding to the logical address;
determining an accuracy of the at least one of the bitmap information or the test data information by comparing the actual defect location with the expected location, a deviation between the actual defect location and the expected location indicating that the at least one of the bitmap information or the test data information is incorrect.
2. The method of claim 1 , wherein the semiconductor device is a wafer.
3. The method of claim 1 , wherein the semiconductor includes logic circuitry and the defect is introduced within the circuitry.
4. The method of claim 1 , wherein detecting the defect at the logical address is carried out using a test probing technique.
5. The method of claim 1 , wherein the laser produces a pulse of laser energy that induces a heating effect having a thermal diffusion length.
6. The method of claim 5 , wherein the laser comprises a pulsed neodymium-doped yttrium aluminum garnet (Nd:YAG) laser.
7. A method of verifying bitmap information or test data information for a semiconductor device, the method comprising:
placing a defect on a semiconductor device at an actual defect location, wherein placing a defect on the semiconductor device is carried out with a laser;
detecting the defect at a logical address;
reviewing at least one of bitmap information or test data information to determine an expected location corresponding to the logical address;
determining an accuracy of the at least one of the bitmap information or the test data information by comparing the actual defect location with the expected location, a deviation between the actual defect location and the expected location indicating that the at least one of the bitmap information or the test data information is incorrect.
8. The method of claim 7 , wherein placing a defect on the semiconductor device includes physically damaging at least a portion of the semiconductor device.
9. The method of claim 7 , wherein the semiconductor device is a wafer.
10. The method of claim 7 , wherein the semiconductor includes logic circuitry and the defect is introduced on the circuitry.
11. The method of claim 7 , wherein detecting the defect at the logical address is carried out using a test probing technique.
12. The method of claim 7 , wherein
the semiconductor device is silicon coated with metal, the metal being on the front side and the silicon being on the back side, and
placing a defect on the semiconductor device includes introducing damage to the metal from the front side.
13. The method of claim 7 , wherein
the semiconductor device is silicon coated with metal, the metal being on the front side and the silicon being on the back side, and
placing a defect on the semiconductor device includes introducing damage to the metal from the back side.
14. A system for verifying bitmap information or test data information for a semiconductor device, the system comprising:
a laser device operable to place a defect on a semiconductor device at an actual defect location;
a device operable to detect the defect at a logical address; and
a processing device operable to:
review at least one of bitmap information or test data information to determine an expected location corresponding to the logical address, and
determine an accuracy of the at least one of the bitmap information or the test data information by comparing the actual defect location with the expected location, a deviation between the actual defect location and the expected location indicating that the at least one of the bitmap information or the test data information is incorrect.
15. The system of claim 14 , wherein the device operable to place a defect on the semiconductor device at an actual defect location physically damages at least a portion of the semiconductor device.
16. The system of claim 14 , wherein the semiconductor device is a wafer.
17. The system of claim 14 , wherein the semiconductor includes logic circuitry and the defect is introduced on the circuitry.
18. The system of claim 14 , wherein the device operable to detect the defect at the logical address is a test probe.
19. The system of claim 14 , wherein
the semiconductor device is silicon coated with metal, the metal being on the front side and the silicon being on the back side, and
the device that places the defect on the semiconductor device introduces damage to the metal from the back side.
20. The system of claim 14 , wherein
the semiconductor device is silicon coated with metal, the metal being on the front side and the silicon being on the back side, and
the device that places the defect on the semiconductor device introduces damage to the metal from the front side.