Integration of germanium photo detector in CMOS processing

1. A method comprising:

forming an N-well in a silicon (Si) substrate;

forming a transistor or resistor in the Si substrate laterally removed from the N-well;

forming an interlayer dielectric (ILD) over the Si substrate and the transistor or resistor;

forming a Si-based dielectric layer on the ILD;

forming a polysilicon (poly-Si) or amorphous silicon (a-Si) layer on the Si-based dielectric layer;

removing a portion of the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well, forming a trench;

forming germanium (Ge) or germanium-silicon (Ge/Si) in the trench; and

removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD.

2. The method according to claim 1 , comprising forming the Si-based dielectric and poly-Si or a-Si layers by blanket deposition.

3. The method according to claim 2 , comprising forming the Si-based dielectric layer of silicon nitride (SiN), silicon dioxide (SiO 2 ), or silicon oxynitride (SiON).

4. The method according to claim 2 , comprising:

forming the Si-based dielectric layer to a thickness of 500 angstroms (Å) to 1,500 Å; and

forming the poly-Si or a-Si layer to a thickness of 600 Å to 2,000 Å.

5. The method according to claim 1 , comprising forming the trench by plasma etching or reactive-ion etching (RIE).

6. The method according to claim 1 , comprising forming the trench to a width of −5 micrometers (μm) to 200 μm.

7. The method according to claim 1 , comprising forming the trench to a depth of 3,500 Å to 5,500 Å.

8. The method according to claim 1 , comprising forming the Ge or Ge/Si in the trench and on the poly-Si or a-Si layer by non-selective epitaxial growth.

9. The method according to claim 8 , comprising:

removing the Ge or Ge/Si and the poly-Si or a-Si layer down to an upper surface of the Si-based dielectric layer by chemical mechanical polishing (CMP); and

removing the Si-based dielectric layer by a wet chemical etch down to the upper surface of the ILD.

10. The method according to claim 1 , further comprising:

forming a doped Si cap layer on the Ge or Ge/Si,

wherein the doped Si cap comprises an in-situ doped Si epilayer or an ex-situ doped poly-Si or a-Si layer, and wherein the doped Si cap layer extends over a portion of the ILD.

11. The method according to claim 10 , further comprising:

forming a second ILD to a thickness of 6,000 Å to 10,000 Å over the ILD and Si cap; and

forming a contact through the second ILD down to the doped Si cap.

12. A method comprising:

forming an N-well and a P-well in a silicon-on-insulator (SOI) substrate;

forming a complementary metal-oxide-semiconductor (CMOS) transistor or resistor on the SOI substrate over the P-well;

forming a first interlayer dielectric (ILD) over the SOI substrate and the CMOS transistor or resistor;

depositing a silicon nitride (SiN) layer on the first ILD;

depositing a polysilicon (poly-Si) or amorphous silicon (a-Si) on the SiN layer;

removing a portion of the SiN layer, the poly-Si or a-Si layer, the first ILD, and the N-well, forming a trench;

epitaxially growing germanium (Ge) or germanium-silicon (Ge/Si) in the trench and over the a-Si or poly-Si;

removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the SiN layer down to an upper surface of the first ILD;

forming a doped silicon (Si) cap layer on the Ge or Ge/Si, with a portion extending over the first ILD;

forming a second ILD over the doped Si cap and on the first ILD; and

forming a plurality of contacts through the second ILD.

13. The method according to claim 12 , comprising depositing the SiN and a-Si or poly-Si layers by blanket deposition.

14. The method according to claim 12 , comprising forming the Ge or Ge/Si with a width of 5 μm to 200 μm and a depth of 3,500 Å to 5,500 Å.