Vertical nanowire based hetero-structure split gate memory
View Patent ↗A memory cell is disclosed. The memory cell includes a vertical base disposed on a substrate. The vertical base includes first and second channels between top and bottom terminals. The memory cell also includes a first gate surrounding the first channel and a second gate surrounding the second channel. The first and second gates form a gate-all-around transistor of the memory cell.
1. A memory cell comprising:
a vertical base disposed on a substrate, the vertical base includes first and second channels between top and bottom terminals;
a first gate surrounding the first channel; and
a second gate surrounding the second channel, wherein the first and second gates form a gate-all-around transistor of the memory cell.
2. The memory cell of claim 1 wherein:
a bottom terminal line is disposed in the substrate coupled with the base; and
a top terminal line is disposed over the base coupled to the top terminal.
3. The memory cell of claim 1 wherein:
the bottom terminal is part of the substrate; and
the base includes the first and second channels and the top terminal.
4. The memory cell of claim 1 wherein
the first gate serves as a select gate;
the second gate serves as a memory gate.
5. The memory cell of claim 4 wherein the select gate is closer to the substrate.
6. The memory cell of claim 1 wherein the first channel and the second channel comprise different crystalline semiconductor materials.
7. The memory cell of claim 6 wherein the first semiconductor material has a higher band gap than the second semiconductor material.
8. The memory cell of claim 6 wherein:
the first semiconductor material comprises silicon; and
the second semiconductor material comprises silicon germanium.
9. The memory cell of claim 7 wherein the second channel comprises a heterogeneous channel having the second semiconductor material adjacent to the first channel and a third semiconductor material.
10. The memory cell of claim 9 wherein:
the first and third semiconductor materials comprise silicon; and
the second semiconductor material comprises silicon germanium.
11. The memory cell of claim 1 comprises:
an intermediate channel between first and second channels with an intermediate gate surrounding the intermediate channel, the intermediate gate serves as a select gate; and
the first and second gates serve as first and second memory gates for a dual bit memory cell.
12. The memory cell of claim 11 wherein:
the first channel comprises a first semiconductor material;
the intermediate channel comprises an intermediate semiconductor material; and
the second channel comprises a second semiconductor material, wherein the intermediate semiconductor material is different form the first and second semiconductor materials.
13. The memory cell of claim 12 wherein the intermediate semiconductor material has a higher band gap than the second semiconductor material.
14. The memory cell of claim 13 wherein:
the first and second semiconductor materials are the same and comprise silicon germanium; and
the intermediate semiconductor material comprises silicon.
15. The memory cell of claim 13 wherein:
the first channel comprises a heterogeneous channel having the first semiconductor material adjacent to the intermediate channel and a third semiconductor material;
the second channel comprises a heterogeneous channel having the second semiconductor material adjacent to the intermediate channel and a fourth semiconductor material.
16. The memory cell of claim 15 wherein:
the third and fourth semiconductor materials are the same and comprise silicon; and
the first and second semiconductor materials are the same and comprise silicon germanium.
17. A method of forming a device comprising:
providing a substrate;
forming a vertical base on the substrate, wherein the base includes first and second channels between top and bottom terminals of a memory cell; and
forming first and second gates surrounding the first and second channels.
18. The method of claim 17 wherein the bottom terminal is part of the substrate.
19. The method of claim 17 wherein:
the first channel comprises a first semiconductor material; and
the second channel comprises a second semiconductor material, forming a heterogeneous base.
20. The method of claim 17 wherein:
forming the vertical base includes an intermediate channel between the first and second channels between the top and bottom terminals; and
forming an intermediate gate surrounding the intermediate channel.