IP Library Granted Patent US 7,928,020
Granted Patent B2
US 7,928,020 · App. 11/862,865 · Granted Apr 19, 2011

Method of fabricating a nitrogenated silicon oxide layer and MOS device having same

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Quick Facts
Patent No.
US 7,928,020
App. No.
11/862,865
Granted
Apr 19, 2011
Kind
B2
Abstract

A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.

Claims (42)

1. A method for fabricating a nitrogen-containing dielectric layer comprising:

a) forming a silicon oxide dielectric layer on a substrate whereby an interface region resides adjacent the substrate and a surface region resides opposite the interface region;

b) introducing nitrogen into the silicon oxide dielectric layer by applying a nitrogen plasma; and

c) annealing the silicon oxide dielectric layer after applying the nitrogen plasma, and

repeating steps b) and c) at least one time to form a nitrogen concentration profile in the silicon oxide dielectric layer,

wherein at least a final annealing step is carried out in an oxygen-containing atmosphere, and

wherein the nitrogen concentration profile is characterized by a bi-modal distribution, such that peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is in proximity to the surface region.

2. The method of claim 1 , wherein steps b) and c) provide a nitrogen-containing silicon oxide comprising about 5 to about 25 atomic % nitrogen.

3. The method of claim 1 , wherein steps b) and c) provide a nitrogen-containing silicon oxide comprising about 5 to about 8 atomic % nitrogen.

4. The method of claim 1 , wherein steps b) and c) provide a nitrogen-containing silicon oxide comprising an equivalent oxide thickness of about 10 to about 20 angstroms.

5. The method of claim 1 , wherein at least a first annealing step is carried out in substantially pure nitrogen atmosphere.

6. The method of claim 1 , wherein at least one annealing step comprises annealing in an N 2 O atmosphere.

7. The method of claim 6 , wherein annealing in an N 2 O atmosphere comprises introducing oxygen radicals into the silicon oxide dielectric layer.

8. The method of claim 1 , wherein forming a silicon oxide dielectric layer comprises rapid thermal oxidation of the substrate in an oxidation atmosphere comprising N 2 O.

9. The method of claim 1 , wherein repeating steps b) and c) comprises repeating steps b) and c) at least three times.

10. The method of claim 1 , wherein applying a nitrogen plasma comprises applying a decoupled plasma nitridation process.

11. The method of claim 1 , wherein introducing nitrogen into the silicon oxide dielectric layer comprises applying a nitrogen plasma for about 7 seconds, and wherein annealing the silicon oxide dielectric layer comprises annealing for about 5 seconds.

12. A method for fabricating a semiconductor device comprising:

a) forming a silicon oxide dielectric layer on a substrate whereby an interface region resides adjacent the substrate and a surface region resides opposite the interface region;

b) introducing nitrogen into the silicon oxide dielectric layer by applying a nitrogen plasma;

c) annealing the silicon oxide dielectric layer after applying the nitrogen plasma, and

repeating steps b) and c) at least one time to form an SiON layer having a nitrogen concentration profile characterized by a bi-modal distribution, such that the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is in proximity to the surface region,

wherein at least a final annealing step is carried out in an oxygen-containing atmosphere; and

d) forming a gate electrode on the SiON layer.

13. A method for fabricating a gate dielectric layer comprising:

forming a nitrogen-containing dielectric layer on a substrate according to the following steps:

a) introducing nitrogen into a silicon oxide dielectric layer by applying a nitrogen plasma; and

b) annealing the silicon oxide dielectric layer after applying the nitrogen plasma, and repeating steps a) and b) at least one time,

wherein at least a final annealing step is carried out in an oxygen-containing atmosphere,

whereby an interface region resides adjacent the substrate and a surface region resides opposite the interface region, wherein the nitrogen-containing dielectric layer has a nitrogen concentration profile characterized by a bi-modal nitrogen concentration distribution, such that peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is in proximity to the surface region.

14. The method of claim 13 , wherein annealing the silicon oxide dielectric layer comprises annealing in an N 2 O atmosphere and introducing oxygen radicals into the silicon oxide dielectric layer.

15. The method of claim 13 , wherein repeating steps b) and c) comprises repeating steps b) and c) at least three times, and wherein at least the first annealing step is carried out in a substantially pure nitrogen atmosphere and at least the final annealing step is carried out in an oxygen-containing atmosphere.

16. The method of claim 12 , wherein forming a gate electrode comprises forming a polysilicon gate electrode.

17. The method of claim 13 , wherein applying a nitrogen plasma comprises applying a decoupled plasma nitridation process.

18. The method of claim 13 , wherein at least the first annealing step is carried out in a substantially pure nitrogen atmosphere.

19. The method of claim 13 , wherein forming a nitrogen-containing dielectric layer comprises forming an SiON layer comprising about 5 to about 25 atomic % nitrogen.

20. The method of claim 13 , wherein forming a nitrogen-containing dielectric layer comprises forming an SiON layer comprising about 5 to about 8 atomic % nitrogen.

21. The method of claim 13 , wherein forming a nitrogen-containing dielectric layer comprises forming an SiON layer having an equivalent oxide thickness of about 10 to about 20 angstroms.

22. A method for fabricating a gate dielectric layer comprising:

forming a silicon oxide layer on a substrate, wherein an interface regions resides adjacent the substrate and a surface region resides opposite the interface region;

introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer and repeating introducing nitrogen and annealing at least one time to form a nitrogen-containing dielectric layer having a bi-modal nitrogen concentration distribution, such that peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is in proximity to the surface region, wherein at least the final annealing step is carried out in an oxygen-containing atmosphere.

23. The method of claim 22 , wherein at least a first annealing step is carried out in a substantially pure nitrogen atmosphere.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
SECURITY AGREEMENT Recorded Nov 27, 2018
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 047660/0203 →
CHANGE OF NAME Recorded Aug 9, 2011
From: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
To: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
Reel/Frame 026723/0879 →
CHANGE OF NAME Recorded Aug 9, 2011
From: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 026723/0908 →