IP Library Granted Patent US 9,287,497
Granted Patent B2
US 9,287,497 · App. 14/295,547 · Granted Mar 15, 2016

Integrated circuits with hall effect sensors and methods for producing such integrated circuits

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Quick Facts
Patent No.
US 9,287,497
App. No.
14/295,547
Granted
Mar 15, 2016
Kind
B2
Abstract

Integrated circuits with a Hall effect sensor and methods for fabricating such integrated circuits are provided. The method includes forming a buried plate layer within a substrate and overlying a substrate base, where the buried plate layer is doped with an “N” type dopant. A cover insulating layer if formed overlying the buried plate layer, and a plurality of contact points are formed adjacent to the cover insulating layer.

Claims (32)

1. A method of producing an integrated circuit comprising:

forming a buried plate layer within a substrate and overlying a substrate base, wherein the buried plate layer is doped with an “N” type dopant;

forming a cover insulating layer overlying the buried plate layer; and

forming a plurality of contact points in the substrate, wherein the plurality of contact points are adjacent to the cover insulating layer, and wherein the plurality of contacts are on four different sides of the cover insulating layer.

2. The method of claim 1 wherein forming the cover insulating layer comprises forming a shallow trench isolation.

3. The method of claim 2 wherein forming the cover insulating layer comprises etching a trench in the substrate and depositing an insulating material in the trench to form the shallow trench isolation.

4. The method of claim 1 wherein forming the cover insulating layer comprises forming an amorphous silicon layer overlying the buried plate layer.

5. The method of claim 1 wherein forming the cover insulating layer comprises oxidizing the substrate to form silicon oxide, wherein the substrate comprises silicon.

6. The method of claim 1 wherein forming the plurality of contact points comprises forming the plurality of contact points adjacent to each of the sides of a square or a rectangle.

7. The method of claim 1 wherein forming the buried plate layer comprises epitaxially growing the substrate overlying the substrate base.

8. The method of claim 1 wherein forming the plurality of contact points comprises implanting “N” type dopant ions into the substrate.

9. The method of claim 1 wherein forming the plurality of contact points comprises:

implanting “N” type dopant ions into the substrate at a conductive zone dopant concentration to form a conductive zone; and

implanting “N” type dopant ions into the conductive zone at a contact point dopant concentration greater than the conductive zone dopant concentration to form the plurality of contact points.

10. The method of claim 1 wherein forming the plurality of contact points comprises forming the plurality of contact points by implanting “N” type dopant ions at a source/drain concentration.

11. A method of producing an integrated circuit comprising:

forming a buried plate layer within a substrate and overlying a substrate base, wherein the buried plate layer comprises an “N” type dopant;

forming a second cover layer overlying the buried plate layer, wherein the second cover layer comprises a “P” type dopant;

forming a first cover layer overlying the second cover layer such that the second cover layer is positioned between the first cover layer and the buried plate layer, and wherein the first cover layer comprises “P” type dopant; and

forming a plurality of contact points on four different sides of the first cover layer.

12. The method of claim 11 wherein forming the buried plate layer comprises implanting “N” type dopant ions into the substrate.

13. The method of claim 11 wherein forming the buried plate layer comprises epitaxially growing the buried plate layer overlying the substrate base.

14. The method of claim 11 wherein forming the plurality of contact points comprises implanting “N” type dopant ions into the substrate.

15. The method of claim 11 wherein forming the plurality of contact points comprises:

implanting “N” type dopant ions into the substrate at a conductive zone dopant concentration to form a conductive zone; and

implanting “N” type dopant ions into the conductive zone at a contact point dopant concentration greater than the conductive zone dopant concentration to form the plurality of contact points.

16. The method of claim 11 wherein forming the second cover layer comprises forming the second cover layer with “P” type dopant ions at a second dopant concentration; and wherein

forming the first cover layer comprises forming the first cover layer with “P” type dopant ions at a first dopant concentration, wherein the first dopant concentration is greater than the second dopant concentration.

17. The method of claim 16 wherein forming the second cover layer comprises forming the second cover layer wherein the second dopant concentration is about the same as a dopant concentration in a high voltage “P” type lowly doped drain; and wherein

forming the first cover layer comprises forming the first cover layer wherein the first dopant concentration is about the same as a source/drain concentration.

18. The method of claim 11 wherein forming the first cover layer comprises implanting “P” type dopant ions at about a source/drain concentration.

19. The method of claim 11 where forming the plurality of contact points comprises forming the plurality of contact points adjacent to each of the sides of a square or a rectangle.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
SECURITY AGREEMENT Recorded Nov 27, 2018
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 047660/0203 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2014
From: TOH, ENG HUAT; LIU, XINFU
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 033026/0200 →